參數(shù)資料
型號(hào): MT9300BV
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數(shù)字傳輸電路
英文描述: Multi-Channel Voice Echo Canceller
中文描述: DATACOM, ISDN ECHO CANCELLER, PBGA208
封裝: 17 X 17 MM, 1.30 MM HEIGHT, MO-192, LBGA-208
文件頁數(shù): 27/39頁
文件大?。?/td> 629K
代理商: MT9300BV
MT9300B
Data Sheet
27
Zarlink Semiconductor Inc.
Power Reset Value
0CH
7
6
5
4
3
2
1
0
NLP
15
NLP
14
NLP
13
NLP
12
NLP
10
NLP
9
NLP
8
NLP
11
Echo Canceller A, Non-Linear Processor Threshold Register 2
Echo Canceller B, Non-Linear Processor Threshold Register 2
Read/Write Address: 19
H
+ Base Address
Read/Write Address: 39
H
+ Base Address
Power Reset Value
E0H
7
6
5
4
3
2
1
0
NLP
7
NLP
6
NLP
5
NLP
4
NLP
2
NLP
1
NLP
0
NLP
3
Echo Canceller A, Non-Linear Processor Threshold Register 1
Echo Canceller B, Non-Linear Processor Threshold Register 1
Read/Write Address: 18
H
+ Base Address
Read/Write Address: 38
H
+ Base Address
This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16 bit 2’s complement linear
value
defaults
to 0B60h = 0.0889 or -21.0 dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and the low
byte is in Register 1.
(NLPTHR)
(NLPTHR)
Power Reset Value
40H
7
6
5
4
3
2
1
0
MU
15
MU
14
MU
13
MU
12
MU
10
MU
9
MU
8
MU
11
Echo Canceller A, Adaptation Step Size (MU) Register 2
Echo Canceller B, Adaptation Step Size (MU) Register 2
Read/Write Address: 1B
H
+ Base Address
Read/Write Address: 3B
H
+ Base Address
Power Reset Value
00H
7
6
5
4
3
2
1
0
MU
7
MU
6
MU
5
MU
4
MU
2
MU
1
MU
0
MU
3
Echo Canceller A, Adaptation Step Size (MU) Register 1
Echo Canceller B, Adaptation Step Size (MU) Register 1
Read/Write Address: 1A
H
+ Base Address
Read/Write Address: 3A
H
+ Base Address
This register allows the user to program the level of MU. MU is a 16 bit 2’s complement value which defaults to 4000h = 1.0
The maximum value is 7FFFh or 1.9999 decimal. The high byte is in Register 2 and the low byte is in Register 1.
(MU)
(MU)
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