- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359235 > MT9160AN1 (Zarlink Semiconductor Inc.) 3 Volt Multi-Featured Codec (MFC) PDF資料下載
參數(shù)資料
| 型號： | MT9160AN1 |
| 廠商： | Zarlink Semiconductor Inc. |
| 元件分類： | Codec |
| 英文描述： | 3 Volt Multi-Featured Codec (MFC) |
| 中文描述： | 3伏多精選編解碼器（MFC）中 |
| 文件頁數(shù)： | 3/33頁 |
| 文件大小： | 527K |
| 代理商： | MT9160AN1 |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁
MT91L60/61
Data Sheet
3
Zarlink Semiconductor Inc.
Figure 2 - Pin Connections
Pin Description
Pin #
20 Pin24 Pin
Name
Description
1
1
V
Bias
Bias Voltage (Output).
(V
DD
/2) volts is available at this pin for biasing external
amplifiers. Connect 0.1
μ
F capacitor to V
SSA
.
Reference Voltage for Codec (Output).
Used internally. Nominally [Vdd/2 - 1.1]
volts. Connect 0.1
μ
F capacitor to V
SSA
.
PWRST
Power-up Reset (Input).
CMOS compatible input with Schmitt Trigger (active low).
2
2
V
Ref
3
4
4
5
IC
Internal Connection.
Tie externally to V
SSD
for normal operation.
A/
μ
/IRQ
A/
μ
- When internal control bit DEn = 0 this CMOS level compatible input pin governs
the companding law used by the filter/Codec;
μ
-Law when tied to V
SSD
and A-Law
when tied to V
DD
. Logically OR’ed with A/
μ
register bit.
IRQ
- When internal control bit DEn = 1 this pin becomes an open-drain interrupt
output signalling valid access to the D-Channel registers in ST-BUS mode.
5
6
6
7
V
SSD
CS
Digital Ground.
Nominally 0 volts.
7
8
Chip Select (Input).
This input signal is used to select the device for microport
data transfers. Active low. CMOS level compatible.
8
10
SCLK
Serial Port Synchronous Clock (Input).
Data clock for microport. CMOS level
compatible.
9
11
DATA 1
Bidirectional Serial Data.
Port for microprocessor serial data transfer. In
Motorola/National mode of operation, this pin becomes the data transmit pin only
and data receive is performed on the DATA 2 pin. Input CMOS level compatible.
10
12
DATA 2
Serial Data Receive.
In Motorola/National mode of operation, this pin is used for
data receive. In Intel mode, serial data transmit and receive are performed on the
DATA 1 pin and DATA 2 is disconnected. Input CMOS level compatible.
11
13
D
out
Data Output.
A high impedance three-state digital output for 8 bit wide channel
data being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent
with the rising edge of the bit clock during the timeslot defined by STB, or according
to standard ST-BUS timing.
M -
VSSA
NC
M +
VBias
VRef
NC
PWRST
IC
VSSD
SCLK
DATA1
DATA2
Din
Dout
HSPKR +
HSPKR -
VDD
CLOCKin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
A/
μ
/IRQ
CS
NC
STB/F0i
NC
M -
VSSA
HSPKR +
HSPKR -
VDD
CLOCKin
M +
VBias
VRef
PWRST
IC
VSSD
SCLK
DATA1
DATA2
Din
Dout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
20
19
18
17
A/
μ
/IRQ
CS
STB/F0i
20 PIN SOIC/SSOP
24 PIN PDIP
M -
VSSA
NC
M +
VBias
VRef
NC
PWRST
IC
VSSD
SCLK
DATA1
DATA2
Din
Dout
HSPKR +
HSPKR -
VDD
CLOCKin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
24
23
22
21
20
19
18
17
A/
μ
/IRQ
CS
NC
STB/F0i
STBd/FOod
24 PIN PDIP/SOIC/SSOP
MT91L60AS/AN
MT91L60AE
MT91L61AE/AS/AN
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT91610 | Programmable Ringing SLIC |
| MT91610AQ | Programmable Ringing SLIC |
| MT91610 | Analog Ringing SLIC |
| MT91610AQ | Analog Ringing SLIC |
| MT9162AN1 | 5 Volt Single Rail Codec |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9160AS | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT9160B | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO2-CMOS 5 Volt Multi-Featured Codec (MFC) |
| MT9160BE | 制造商:Microsemi Corporation 功能描述:MULTI-FEATURED CODEC 24PDIP - Rail/Tube |
| MT9160BN | 制造商:Microsemi Corporation 功能描述: |
| MT9160BS | 制造商:Microsemi Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。