參數(shù)資料
型號: MT9160AN1
廠商: Zarlink Semiconductor Inc.
元件分類: Codec
英文描述: 3 Volt Multi-Featured Codec (MFC)
中文描述: 3伏多精選編解碼器(MFC)中
文件頁數(shù): 22/33頁
文件大小: 527K
代理商: MT9160AN1
MT91L60/61
Data Sheet
22
Zarlink Semiconductor Inc.
AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
* Note: TxINC, refer to Control Register 1, address 00h.
AC Characteristics
for A/D (Transmit) Path
-
0 dBm0 = A
Lo3.17
- 3.17 dB
=
1.027 V
rms
for
μ
-Law and
0 dBm0 = A
Lo3.14
-
3.14 dB
=
1.067 V
rms
for A-Law, at the Codec. (V
Ref
= 0.4 V and V
Bias
=1.5 volts.)
Characteristics
Sym.
Min.
Typ.
Max.
Units
Test Conditions
1
Analog input equivalent to
overload decision
A
Li3.17
A
Li3.14
4.246
4.4
Vp-p
Vp-p
μ
-Law
A-Law
Both at Codec
2
Absolute half-channel gain
M ± to Dout
G
AX1
G
AX2
5.4
14.7
6.0
15.3
6.6
15.9
dB
dB
Transmit filter gain=0 dB
setting.
TxINC = 0*
TxINC = 1*
@1020 Hz
Tolerance at all other transmit
filter settings
(1 to 7 dB)
-0.2
±0.1
+0.2
dB
3
Gain tracking vs. input level
ITU-T G.714 Method 2
G
TX
-0.3
-0.6
-1.6
0.3
0.6
1.6
dB
dB
dB
3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
4
Signal to total Distortion vs. input
level.
ITU-T G.714 Method 2
D
QX
35
29
24
dB
dB
dB
0 to -30 dBm0
-40 dBm0
-45 dBm0
5
Transmit Idle Channel Noise
N
CX
N
PX
G
RX
13
-70.5
16
-69
dBrnC0
dBm0p
μ
-Law
A-Law
6
Gain relative to gain at 1020 Hz
<50 Hz
60 Hz
200 Hz
300 - 3000 Hz
3000-3300 Hz
3300 Hz
3400 Hz
4000 Hz
4600 Hz
>4600 Hz
-0.25
-0.9
-0.9
-1.2
-45
-0.2
-0.6
-23
-41
-25
-30
0.0
0.25
0.25
0.25
0.25
-12.5
-25
-25
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
7
Absolute Delay
D
AX
360
ms
at frequency of minimum
delay
8
Group Delay relative to D
AX
D
DX
750
380
130
750
ms
ms
ms
ms
500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz
9
Power Supply Rejection
f=1020 Hz
PSSR
30
50
dB
±100 mV peak signal on
V
DD
μ
-law
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