MT91L60/61
Data Sheet
13
Zarlink Semiconductor Inc.
PWRST/Software Reset (Rst)
While the MT91L60/61 is held in PWRST no device control or functionality is possible. While in software reset
(Rst=1, address 03h) only the microport is functional. Software reset can only be removed by writing the Rst bit low
or by performing a hardware PWRST. While the Rst bit is high, the other bits in Control Register 1 are held low and
cannot be reprogrammed. Therefore to modify Control Register 1 the Rst bit must first be written low, followed by a
2nd write operation which writes the desired data. This avoids a race condition between clearing the reset bit and
the writing of the other bits in Control Register 1.
After a Power-up reset (PWRST) or software reset (Rst) all control bits assume their "Power Reset Value" default
states;
μ
-Law coding, 0 dB Rx and 6dB Tx gains and the device powered up in SSI mode 2048 kb/s operation with
Dout tri-stated while there is no strobe active on STB. If a valid strobe is supplied to STB, then Dout will be active,
during the defined channel.
To attain complete power-down from a normal operating condition, write PDFDI = 1 and PDDR = 1 (Control
Register 1, address 03h) or set the PWRST pin low.
Table 2 - 3V Multi-featured Codec Register Map
Note: Bits marked "-" are reserved bits and should be written with logic "0"
00
RxINC
RxFG
2
RxFG
1
RxFG
0
TxINC
TxFG
2
TxFG
1
TxFG
0
Gain Control
Register 1
01
-
-
-
-
-
STG
2
STG
1
STG
0
Gain Control
Register 2
02
-
-
-
-
-
-
-
DrGain
Path Control
03
PDFDI
PDDR
RST
-
T
x
Mute
R
x
Mute
T
x
Bsel
R
x
Bsel Control Register 1
04
CEN
DEN
D8
A/
μ
Smag/
ITU-T
CSL
2
CSL
1
CSL
0
Control Register 2
05
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
C-Channel
Register
06
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D-Channel
Register
07
-
-
-
-
PCM/
ANALOG
loopen
-
-
Loop Back