- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383645 > MT90810 (Mitel Networks Corporation) Flexible MVIP(Multi-Vendor Integration Protocol) Interface Circuit(彈性MVIP接口電路) PDF資料下載
參數(shù)資料
| 型號(hào)： | MT90810 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Flexible MVIP(Multi-Vendor Integration Protocol) Interface Circuit(彈性MVIP接口電路) |
| 中文描述： | 柔性MVIP（多廠商集成協(xié)議）接口電路（彈性MVIP接口電路） |
| 文件頁(yè)數(shù)： | 8/33頁(yè) |
| 文件大?。?/td> | 176K |
| 代理商： | MT90810 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)當(dāng)前第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)
MT90810
Preliminary Information
2-176
Figure 5 - Jitter Transfer Function of the Analog PLL
Jitter
Attenuation
(dB)
16
14
12
10
8
6
4
2
1
10
100
1K
10K
100K
Frequency, log scale (Hz)
In these modes, the FMIC state machine is
synchronized to the external 8kHz input selected,
that is, the state machine output 8kHz FRAME and
F0b signals are phase aligned with the external 8kHz
input as well as frequency locked. Here lies the
difference between these modes (5, 6 and 7) and the
above mentioned modes (1, 2 and 3). In these
modes, the external 8kHz input signal is used to
synchronize the FMIC state machine.
In modes 5,6 and 7, the external clock X1 must be
16.384MHz. This is required for proper operation of
the digital PLL.
The FMIC becomes MVIP master when MVIP_MST
bit is set in the Control/Status register.
5. PLL Jitter Performance
To measure the intrinsic jitter of the analog PLL, the
FMIC is set to slave mode, slave to a clean MVIP C4
clock (no jitter). A resulting jitter of 0.004UI p-p is
measured on the C2o clock.
The jitter transfer function of the analog PLL, which
is the ratio of the output jitter to the input jitter, is
shown in “Figure 5 - Jitter Transfer Function of the
Analog PLL” . The measurements are made with a
controlled sinusoidal jitter modulating the MVIP C4
clock.
To measure the intrinsic jitter of the two PLLs
combined, the FMIC is set to master mode, slave to
a clean external 8kHz clock SEC8K (no jitter). A
resulting jitter of 0.206UI p-p is measured on the C2o
clock.
Jitter transfer function of the digital PLL and analog
PLL combination is determined primarily by the
digital PLL. The digital PLL is essentially a digital
sampler which samples on the nearest rising or
falling edge of its 16MHz clock and therefore has a
60ns jitter on the output.
Please note that the digital PLL and analog PLL
combination may not meet some international
standards for jitter performance. In cases where
strict idle jitter specifications must be met, an
external custom PLL may be required and the
internal analog PLL should be disabled (refer to PLL
Diagnostic section for further details).
6. Local Output Clock Control
The FMIC provides four output clocks which are
always driven off of the device. The FRAME output
clock has a duty cycle and period equal to the MVIP
F0 signal. The CLK2 and CLK4 output clocks are
identical to the MVIP C2 and C4 clocks, respectively.
The CLK8 output provides a 8.192MHz clock. The
frame pulse and output clocks may be used to
provide framing and clocking signals to serial
interfaces other than ST-BUS, such as, GCI bus.
Timing diagrams and parameters are provided in
Figures 19 and 20 along with the associated table.
The local output clock control register is defined in
Table 11 - “Local Clock Control (LOC_CLK)
Register”. The register allows the user to program
the polarity of the four local output clocks. In
addition, the register contains four read-only bits
which indicate the logic levels on EX_8KA, EX_8KB,
DACK0 and DACK1 input pins of the device.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT90812 | Integrated Digital Switch (IDX)(集成數(shù)字開(kāi)關(guān)) |
| MT90840AK | Distributed Hyperchannel Switch |
| MT90840AP | Distributed Hyperchannel Switch |
| MT9085B | PAC - Parallel Access Circuit(并行存取電路) |
| MT9092 | Digital Telephone with HDLC(數(shù)字電話（帶高階數(shù)據(jù)鏈路控制HDLC）) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90810AK | 制造商:Microsemi Corporation 功能描述: |
| MT90812 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Integrated Digital Switch (IDX) |
| MT90812AL | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays |
| MT90812AL1 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 192 X 192 16.384MBPS 5V 64MQFP - Trays 制造商:Microsemi Corporation 功能描述:PB FREE INTEGRATED DIGITAL SWITCH |
| MT90812AP | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Integrated Digital Switch (IDX) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。