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參數(shù)資料
| 型號： | MT90810 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Flexible MVIP(Multi-Vendor Integration Protocol) Interface Circuit(彈性MVIP接口電路) |
| 中文描述： | 柔性MVIP（多廠商集成協(xié)議）接口電路（彈性MVIP接口電路） |
| 文件頁數(shù)： | 15/33頁 |
| 文件大小： | 176K |
| 代理商： | MT90810 |
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Preliminary Information
MT90810
2-183
Figure 7 - Serial Mode (SER_MODE) Register
Mode [bits]
Description
X1 =
Comments
0 [00]
1 [01]
2 [10]
3 [11]
16.384MHz
8.192MHz
4.096MHz
RESERVED
Table 10 - XCLK_SEL bits (control divide ratio of X1 clock)
X1 must be 16.384MHz when PLL is in modes 1-3 or 5-7
Bit
Name
Bit Function
7
6
5
4
3
2
1
0
DACK1
DACK0
EX8KB
EX8KA
INV_CLK8
INV_CLK4
INV_CLK2
INV_FRM
Read-only, reads logic value on DACK1 pin
Read-only, reads logic value on DACK0 pin
Read-only, reads logic value on EX8KB pin
Read-only, reads logic value on EX8KA pin
When set, inverts 8.192MHz CLK8 output pin
When set, inverts 4.096MHz CLK4 output pin
When set, inverts 2.048MHz CLK2 output pin
When set, inverts FRAME output signal
Table 11 - Local Clock Control (LOC_CLK) Register
Mode
[bits]
0 [00]
Description
Multiplexing of streams onto pins
LDI/O[str] where str=stream (0-3)
2MHz streams
All local streams are configured to run at 2MHz.
Each channel occupies a 2Mb/s timeslot of 3.9
μ
s.
1 [01]
4MHz streams
local streams 0&1 are multiplexed onto pin LDI/O[0]
local streams 2&3 are multiplexed onto pin LDI/O[2]
Each channel occupies a 4Mb/s timeslot of 1.95
μ
s.
LDI/O[0]
(4MHz, 64
channels)
stream0, ch0
stream1, ch0
stream0, ch1
stream1, ch1
LDI/O[2]
(4MHz, 64
channels)
stream2, ch0
stream3, ch0
stream2, ch1
stream3, ch1
channel 0
channel 1
channel 2
channel 3
etc....
Table 12 - SER_CNFG bits (control configuration of local serial streams)
7
6
5
4
3
2
1
0
SER_CNFG
RESERVED
LDI/O[0] = local stream 0
LDI/O[1] = local stream 1
LDI/O[2] = local stream 2
LDI/O[3] = local stream 3
2MHz,
32 channels
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