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參數(shù)資料
| 型號(hào)： | MT90810 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Flexible MVIP(Multi-Vendor Integration Protocol) Interface Circuit(彈性MVIP接口電路) |
| 中文描述： | 柔性MVIP（多廠商集成協(xié)議）接口電路（彈性MVIP接口電路） |
| 文件頁(yè)數(shù)： | 13/33頁(yè) |
| 文件大小： | 176K |
| 代理商： | MT90810 |
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Preliminary Information
MT90810
2-181
Figure 6 - Clock Control (CLK_CNTRL) Registe
r
Bits
Bit Function
7:6
Auto increment/decrement mode
[00] Normal Mode - indirect address not auto incremented
[01] Auto increment indirect address after indirect read of IDR
[10] Auto increment indirect address after indirect write of IDR
[11] Auto increment indirect address after indirect read or write of IDR
Selects the memory space:
[00] FMIC Control Registers
[01] Data Memory
[10] Connection Memory Low Byte
[11] Connection Memory High Byte
Reserved
Bit 8 of the Indirect Address
Table 5 - Address Mode Register [10]
5:4
3:1
0
Bits
Bit Function
7:0
All bits are written into the indirect address location specified by the LAR and AMR registers.
If auto increment on write/read is enabled, and connection memory is selected, then consecutive
writes/reads to/from the IDR will toggle between selection of high byte and low byte connection
memory.
Table 6 - Indirect Data Register [1]
Indirect Address
Name
Function
0
1
2
3
4
5
6
7
CLK_CNTRL
LOC_CLK
SER_MODE
Clock Control Register
Local Output Clock Control
Local Serial Configuration Register
RESERVED
Frame Group A start register
Frame Group A mode register
Frame Group B start register
Frame Group B mode register
RESERVED
Chip diagnostic bits
FRMA_STRT
FRMA_MODE
FRMB_STRT
FRMB_MODE
8:11
12
13:511
DIAG_REG
RESERVED
Table 7 - FMIC Control Register (read/write)
7
6
5
4
3
2
1
0
XCLK_SEL
PLL_MODE
EN_SEC8K
SEL_S8K
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