參數(shù)資料
型號: MT90840AP
廠商: Mitel Networks Corporation
英文描述: Distributed Hyperchannel Switch
中文描述: 分布式Hyperchannel開關(guān)
文件頁數(shù): 1/4頁
文件大?。?/td> 98K
代理商: MT90840AP
2-189
Features
Time-slot interchange function between 8 pairs
of ST-BUS/GCI/MVIP streams (512 channels)
and a Parallel Data Port (PDP)
Supports star, point to point connections and
unidirectional or bidirectional ring topologies for
distributed systems
Input to Output Bypass function with minimum
delay for shared ring applications
Provides an internal latency adjustment buffer
for ring applications
Parallel port data rates up to 19.44Mbyte/s
Programmable data rates on the serial port side
(2.048 Mb/s, 4.096 Mb/s or 8.192 Mb/s)
Unidirectional Parallel switching mode for up to
2430 channels non-blocking
Per-channel direction control on the serial port
side
Per-channel message mode and high-
impedance control on both parallel and serial
port sides
8-bit multiplexed port compatible with Intel and
Motorola microcontrollers
Guarantees frame integrity when switching
wideband channels such as ISDN H0 channel
Provides external control lines allowing the fast
parallel interface to be shared with other
devices
Special diagnostic alarm functions for statistical
analysis
JTAG boundary scan
Applications
Bridging ST-BUS/MVIP buses to high speed
Time Division Multiplex backplanes at SONET
rates (STS-1/3)
High speed isochronous backbones for
distributed PBX and Local Area Network
systems
Switch platforms of up to 2430 channels with
guaranteed frame integrity for wideband
channels
Serial bus control and monitoring
Data multiplexer
High speed communications interface
Isochronous switching/multiplexing to support
IEEE 802.9 standards
ISSUE 1
June 1995
Ordering Information
MT90840AK
MT90840AP
-40°C to 85°C
100 Pin PQFP
84 Pin PLCC
Figure 1 - Functional Block Diagram
MT90840
Distributed Hyperchannel Switch
Advance Information
DSi[0:7]
DSo[0:7]
WR/
R/W
JTAG
Microprocessor Interface
AD[0:7]ALE
RD/
DS
CS
DTACK
PDo0-7
TDI
TCK
S-P
&
P-S
INT
EXTERNAL
CONTROL
CT0
CT1
CT3
PDi0-7
RECEIVE PATH
DATA & CONN
MEMORIES
TRANSMIT PATH
DATA & CONN
MEMORIES
PARALLEL
PORT
INTERFACE
RESET
RECEIVE
LATENCY
BUFFER
SERIAL PORT TIMING
CONTROL
PARALLEL PORT TIMING
CONTROL
PPFRo
PCKT
PPFRi
PCKR
C4OUT
C4REF1
C4REF2
FO
Serial
Data
Port
Parallel
Data
Port
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