參數(shù)資料
型號： MT90810
廠商： Mitel Networks Corporation
英文描述： Flexible MVIP(Multi-Vendor Integration Protocol) Interface Circuit(彈性MVIP接口電路)
中文描述： 柔性MVIP（多廠商集成協(xié)議）接口電路（彈性MVIP接口電路）
文件頁數(shù)： 7/33頁
文件大?。?/td> 176K
代理商： MT90810
Preliminary Information
MT90810
2-175
Figure 4 - Clock Control Functional Block Diagram
SEC8K
EX_8KA
EX_8KB
C4b
X1
F0b
Digital
PLL
16MHz
div 4
div 2
XCLK_SEL
0
1
2
PLL_MODE
1, 5
2, 6
3, 7
PLL_MODE
X2
Jittery 4.096MHz
60ns peak jitter
(sampler)
Phase
Comparator
VCO
External 8kHz
div 4
8kHz
0
4
up/
down
PLL_LO
PLL_LI
external
loop
filter
External
16MHz Crystal
SEC8K
EX_8KA
EX_8KB
FRAME
EN_SEC8K
SEL_S8K
0
1
2
CLK8
C4b
CLK4
C2o
CLK2
FRAME
F0b
div
by 2
@32MHz
16MHz
4.096MHz
Analog PLL
FMIC
state
machine
and Tables 8 to 10. The clock circuitry (PLLs and
state machine) operates in eight different modes.
1. FMIC as Timing Master (Mode 0)
The FMIC is configured as the timing master
(CLK_CNTRL register cleared, PLL mode 0
selected) after reset. The external 16.384MHz input
is divided by four and used as the input to the analog
PLL so the internal master clock is phase locked to
the 16.384MHz oscillator. The FMIC state machine is
free-running and does not synchronize to any
external 8kHz source.
In this mode, the XLCK_SEL bits of the clock control
register can be programmed to accommodate an
8.192MHz or 4.096MHz external clock instead of the
default 16.384MHz.
The FMIC becomes MVIP master when MVIP_MST
bit is set in the Control/Status register. This mode
can be used when the FMIC chip is to become timing
master in a system which has no digital network
connections (T1 or E1).
2. FMIC as MVIP Slave (Mode 4)
When this mode is selected, MVIP C4 clock is
selected as the input to the analog PLL. The FMIC
internal master clock is then synchronized to the
MVIP bus timing. The FMIC state machine is also
synchronized to the MVIP F0 framing signal.
The MVIP_MST bit in the Control/Status register
should never be set when the device is in mode 4 as
the FMIC is entirely slave to the MVIP bus timing.
3. FMIC as MVIP Master (Mode 1,2,3)
In modes 1 through 3, the output of the device’s
digital PLL is selected as the input to the analog PLL.
The source to the digital PLL is selected as either
SEC8K, EX_8KA or EX_8KB depending on the
particular mode (1, 2 or 3) chosen.
In these modes, the FMIC state machine is not
synchronized to the external 8kHz input selected,
that is, the state machine output 8kHz FRAME and
F0b signals may not be phase aligned with the
external 8kHz input but will always be frequency
locked.
In modes 1, 2 and 3, the external clock X1 must be
16.384MHz. This is required for proper operation of
the digital PLL.
The FMIC becomes MVIP master when MVIP_MST
bit is set in the Control/Status register.
4. FMIC as MVIP Master (Mode 5,6,7)
In modes 5 through 7, the output of the device’s
digital PLL is selected as the input to the analog PLL.
The source to the digital PLL is selected as either
SEC8K, EX_8KA or EX_8KB depending on the
particular mode (5, 6 or 7) chosen.
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