參數(shù)資料
型號(hào)： MT90401AB1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 數(shù)字傳輸電路
英文描述： SONET/SDH System Synchronizer
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80
封裝： 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BEC, LQFP-80
文件頁(yè)數(shù)： 25/38頁(yè)
文件大?。?/td> 650K
代理商： MT90401AB1
MT90401
Data Sheet
25
Zarlink Semiconductor Inc.
5.5 Output Phase Adjustment
Two control registers are available to program the output phase offset of the generated clocks. All 16.384 MHz
derived outputs clocks, F16o, F80, F0o, C16o, C8o, C4o and C2o can be collectively shifted up to 125
microseconds with a step size of 60 nS with respect to the input reference by programming the Set Delay Word 1
and Set Delay Word 2 registers.
Control and Status Registers
Address
(A
6
A
5
A
4
A
3
A
2
A
1
A
0
)
Register
Read/
Write
Function
00H (Table 6)
Control Register 1
Read/
Write
RSEL, FS2, FS1, MS2, MS1, SONET/SDH
FLOCK, TCLR
01H (Table 7)
Status Register 1
Read
Only
PRIOOR, SECOOR, LOCK, HOLDOVER,
RSV, FLim, RSV, RSV
02H
Reserved
Read
Only
03H
Reserved
Read
Only
04H (Table 8)
Control Register 2
Read/
Write
E3/DS3/OC3,
RSV=0, RSV=0, RSV=0, RSV=0.
E3/DS3,
RSV=0,
RSV=0,
05H
Reserved
Read
/Write
Set all bits to zero.
06H (Table 9)
Set Delay Word 2
Read/
Write
RSV=0, RSV=0, RSV=0, RSV=0, OffEn,
C16OCNT10,C16OCNT9, C16OCNT8
07H (Table 10)
Set Delay Word 1
Read/
Write
C16OCNT7-0
08H
Reserved
Read/
Write
Set all bits to zero.
09H
Reserved
Read
Only
0AH
Reserved
Read
Only
0BH
Reserved
Read
Only
0CH
Reserved
Read
Only
0DH
Reserved
Read
Only
Table 5 - Register Map
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