參數(shù)資料
型號(hào)： MT90401AB1
廠商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： SONET/SDH System Synchronizer
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80
封裝： 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BEC, LQFP-80
文件頁(yè)數(shù)： 21/38頁(yè)
文件大?。?/td> 650K
代理商： MT90401AB1
MT90401
Data Sheet
21
Zarlink Semiconductor Inc.
Figure 12 - Control State Diagram
3.4 Frequency Accuracy
Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an
external reference, but is operating in a free running mode. For the MT90401, the Freerun accuracy is equal to the
Master Clock (C20i) accuracy.
3.5 Holdover Accuracy
Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external
reference signal, but is operating using storage techniques. For the MT90401, the storage value is determined
while the device is in Normal Mode and locked to an external reference signal. The initial frequency offset of the
MT90401 in Holdover Mode is +20 x 10
-9
. This is more accurate than Telcordia’s GR-1244-CORE stratum 3
requirements of +50 x 10
-9
. Once the MT90401 has transitioned into Holdover Mode, holdover stability is
determined by the stability of the 20 MHz Master Clock Oscillator.
The absolute Master Clock (C20i) accuracy of the MT90401 does not affect Holdover accuracy, but the change in
C20i accuracy while in Holdover Mode does.
Phase Re-Alignment
Phase Continuity Maintained (without TIE Corrector Circuit)
Phase Continuity Maintained (with TIE Corrector Circuit)
NOTES:
(XXX)
{A}
Movement to Normal State from any state requires a valid input signal
MS2 MS1 RSEL
Invalid Reference Signal
{A
{A}
S0
Freerun
(10X)
S2H
Holdover
Secondary
(011)
S1H
Holdover
Primary
(010)
S2
Normal
Secondary
(001)
S1
Normal
Primary
(000)
(PCCi=0)
(PCCi=1)
S1A
Auto-Holdover
Primary
S2A
Auto-Holdover
Secondary
PCCi-0
PCCi-1
In the case where 19.44 MHz input reference clocks are
selected (FS2,FS1 = 00) the MT90401 may latch
inaccurate phase reading during transition between
states: S1A>>S1 and S2A>>S2 which may cause
frequency step exceeding ±4.6 ppm and longer than 100
sec lock time.
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