參數資料
型號: MT90401AB1
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 數字傳輸電路
英文描述: SONET/SDH System Synchronizer
中文描述: ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80
封裝: 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BEC, LQFP-80
文件頁數: 15/38頁
文件大?。?/td> 650K
代理商: MT90401AB1
MT90401
Data Sheet
15
Zarlink Semiconductor Inc.
1.7 State Machine Control
An internal state machine can be enabled to control the TIE Corrector Circuit as shown in Figure 1. In hardware
mode, control is based on the logic levels at the control inputs RSEL, MS1, MS2 and PCCi (See Figure 6). In
Microport mode, control is based on the state of control bits RSEL, MS1 and MS2 and the PCCi pin. When
switching from Primary Holdover to Primary Normal, the TIE Corrector Circuit is enabled when PCCi = 1, and
disabled when PCCi = 0.
All state machine changes occur synchronously on the rising edge of F8o. See the Control and Mode of Operation
section for full details.
Figure 6 - Control State Machine Block Diagram
1.8 Master Clock
The MT90401 uses an external oscillator as the master timing source. For recommended master timing circuits,
see the Applications - Master Clock section.
2.0 Control and Mode of Operation
The MT90401 has three possible modes of operation, Normal, Holdover and Freerun.
In hardware mode the Mode/Control Select pins MS2 and MS1 select the mode and method of control as shown in
Table 3.
The active reference input (PRI or SEC) is selected by the RSEL pin as shown in Table 2. Refer to Table 4 and
Figure 12 for details of the state change sequences.
RSEL
Input Reference
0
PRI
1
SEC
Table 2 - Input Reference Selection
MS2
MS1
Mode
0
0
NORMAL
0
1
HOLDOVER
1
0
FREERUN
1
1
Reserved
Table 3 - Operating Modes and States
MS1
MS2
To
Reference
Select MUX
To TIE
Corrector
Enable
Control
State Machine
To DPLL
State
Select
PCCi
RSEL
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