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參數(shù)資料
| 型號： | MT58L128L36D1 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 128K x 36，3.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb，3.3V輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| 中文描述： | 128K的x 36,3.3六/輸出流水線，雙氰胺SyncBurst的SRAM（4MB，在3.3V的輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲器） |
| 文件頁數(shù)： | 21/24頁 |
| 文件大小： | 425K |
| 代理商： | MT58L128L36D1 |
21
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1_2.p65 – Rev 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
PRELIMINARY
READ/WRITE TIMING
6
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A2
tCEH
tCES
BWE#,
BWa#-BWd#
(NOTE 4)
Q
High-Z
ADV#
Single WRITE
D(A3)
A4
A5
A6
D(A5)
D(A6)
D
BURST READ
Back-to-Back READs
(NOTE 5)
High-Z
Q(A2)
Q(A1)
Q(A4)
Q(A4+1)
Q(A4+2)
tWH
tWS
Q(A4+3)
tOEHZ
tDH
tDS
tOELZ
(NOTE 1)
tKQLZ
tKQ
Back-to-Back
WRITEs
A1
DON’T CARE
UNDEFINED
A3
NOTE:
1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
6. Timing is shown assuming that the device was not enabled before entering into this sequence.
-6
-7.5
-10
SYMBOL
t
ADSS
t
WS
t
DS
t
CES
t
AH
t
ADSH
t
WH
t
DH
t
CEH
MIN
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
MAX
MIN
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
MAX
MIN
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE TIMING PARAMETERS
-6
-7.5
-10
SYMBOL
t
KC
f
KF
t
KH
t
KL
t
KQ
t
KQLZ
t
OELZ
t
OEHZ
t
AS
MIN
6.0
MAX
MIN
7.5
MAX
MIN
10
MAX
UNITS
ns
MHz
ns
ns
ns
ns
ns
ns
ns
166
133
100
2.3
2.3
2.5
2.5
3.0
3.0
3.5
4.0
5.0
0
0
0
0
1.5
0
3.5
4.2
4.5
1.5
1.5
2.0
相關PDF資料 |
PDF描述 |
|---|---|
| MT58L128L32P1 | 128K x 32，Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L128L36P1 | 128K x 36，Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L128V32P1 | 128K x 32， Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L256L18P1 | 256K x 18,Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L256V18P1 | 256K x 18，Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT58L128L36D1T-10 | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L128L36F1 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:4Mb: 256K x 18, 128K x 32/36 FLOW-THROUGH SYNCBURST SRAM |
| MT58L128L36F1T-10 | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 4M-Bit 128K x 36 10ns 100-Pin TQFP 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MT58L128L36F1T-10 TR | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V |
| MT58L128L36F1T-8.5 | 制造商:Cypress Semiconductor 功能描述:128KX36 SRAM PLASTIC TQFP 3.3V 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Micron Technology Inc 功能描述: |
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