參數(shù)資料
型號(hào): MT58L128L36D1
廠商: Micron Technology, Inc.
英文描述: 128K x 36,3.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb,3.3V輸入/輸出,流水線式,雙循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
中文描述: 128K的x 36,3.3六/輸出流水線,雙氰胺SyncBurst的SRAM(4MB,在3.3V的輸入/輸出,流水線式,雙循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
文件頁(yè)數(shù): 17/24頁(yè)
文件大?。?/td> 425K
代理商: MT58L128L36D1
17
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1_2.p65 – Rev 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
PRELIMINARY
Q
50
V = 1.5V
Z = 50
Figure 1
LOAD DERATING CURVES
Micron 256K x 18, 128K x 32, and 128K x 36
SyncBurst SRAM timing is dependent upon the capaci-
tive loading on the outputs.
Consult the factory for copies of I/O current versus
voltage curves.
Q
351
317
5pF
+3.3V
Figure 2
AC TEST CONDITIONS
Input pulse levels.................. V
IH
= (V
DD
/2.2) + 1.5V
.................... V
IL
= (V
DD
/2.2) - 1.5V
Input rise and fall times..................................... 1ns
Input timing reference levels ......................V
DD
/2.2
Output reference levels ............................V
DD
Q/2.2
Output load ............................. See Figures 1 and 2
Output Load Equivalents
相關(guān)PDF資料
PDF描述
MT58L128L32P1 128K x 32,Pipelined, SCD SyncBurst SRAM(4Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
MT58L128L36P1 128K x 36,Pipelined, SCD SyncBurst SRAM(4Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
MT58L128V32P1 128K x 32, Pipelined, SCD SyncBurst SRAM(4Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
MT58L256L18P1 256K x 18,Pipelined, SCD SyncBurst SRAM(4Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
MT58L256V18P1 256K x 18,Pipelined, SCD SyncBurst SRAM(4Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
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