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參數(shù)資料
| 型號： | MT46H256M32L2JV-75IT:A |
| 元件分類： | DRAM |
| 英文描述： | 256M X 32 DDR DRAM, 6 ns, PBGA168 |
| 封裝： | 12 X 12 MM, GREEN, PLASTIC, VFBGA-168 |
| 文件頁數(shù)： | 73/106頁 |
| 文件大?。?/td> | 3431K |
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READ Operation
READ burst operations are initiated with a READ command, as shown in Figure 19
(page 47). The starting column and bank addresses are provided with the READ com-
mand, and auto precharge is either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is precharged at the completion of the
burst. For the READ commands used in the following illustrations, auto precharge is
disabled.
During READ bursts, the valid data-out element from the starting column address will
be available following the CL after the READ command. Each subsequent data-out ele-
ment will be valid nominally at the next positive or negative clock edge. Figure 31
(page 70) shows general timing for each possible CL setting.
DQS is driven by the device along with output data. The initial LOW state on DQS is
known as the read preamble; the LOW state coincident with the last data-out element is
known as the read postamble. The READ burst is considered complete when the read
postamble is satisfied.
Upon completion of a burst, assuming no other commands have been initiated, the DQ
will go to High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out
window hold), and the valid data window is depicted in Figure 38 (page 77) and Fig-
tAC (data-out transition skew to CK) is depicted in Figure 40 (page 79).
Data from any READ burst can be truncated by a READ or WRITE command to the
same or alternate bank, by a BURST TERMINATE command, or by a PRECHARGE com-
mand to the same bank, provided that the auto precharge mode was not activated.
Data from any READ burst can be concatenated with or truncated with data from a sub-
sequent READ command. In either case, a continuous flow of data can be maintained.
The first data element from the new burst either follows the last element of a completed
burst or the last desired data element of a longer burst that is being truncated. The new
READ command should be issued x cycles after the first READ command, where x
equals the number of desired data element pairs (pairs are required by the 2n-prefetch
architecture). This is shown in Figure 32 (page 71).
A READ command can be initiated on any clock cycle following a previous READ com-
mand. Nonconsecutive read data is shown in Figure 33 (page 72). Full-speed random
read accesses within a page (or pages) can be performed as shown in Figure 34
Data from any READ burst can be truncated with a BURST TERMINATE command, as
shown in Figure 35 (page 74). The BURST TERMINATE latency is equal to the READ
(CAS) latency; for example, the BURST TERMINATE command should be issued x cy-
cles after the READ command, where x equals the number of desired data element pairs
(pairs are required by the 2n-prefetch architecture).
Data from any READ burst must be completed or truncated before a subsequent WRITE
command can be issued. If truncation is necessary, the BURST TERMINATE command
must be used, as shown in Figure 36 (page 75). A READ burst can be followed by, or
truncated with, a PRECHARGE command to the same bank, provided that auto pre-
charge was not activated. The PRECHARGE command should be issued x cycles after
the READ command, where x equals the number of desired data element pairs. This is
shown in Figure 37 (page 76). Following the PRECHARGE command, a subsequent
2Gb: x16, x32 Mobile LPDDR SDRAM
READ Operation
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
69
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
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