參數(shù)資料
型號(hào)： MT46H256M32L2JV-75IT:A
元件分類(lèi)： DRAM
英文描述： 256M X 32 DDR DRAM, 6 ns, PBGA168
封裝： 12 X 12 MM, GREEN, PLASTIC, VFBGA-168
文件頁(yè)數(shù)： 50/106頁(yè)
文件大小： 3431K
Figure 20: WRITE Command
CS#
WE#
CAS#
RAS#
CKE
Column
A10
BA0, BA1
HIGH
EN AP
DIS AP
Bank
CK
CK#
Don’t Care
Address
Note: 1. EN AP = enable auto precharge; DIS AP = disable auto precharge.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or
the open row in all banks. The bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is issued. Input A10 determines
whether one or all banks will be precharged, and in the case where only one bank is
precharged, inputs BA0 and BA1 select the bank. Otherwise, BA0 and BA1 are treated as
“Don’t Care.” After a bank has been precharged, it is in the idle state and must be activa-
ted prior to any READ or WRITE commands being issued to that bank.
2Gb: x16, x32 Mobile LPDDR SDRAM
Commands
PDF: 09005aef83a73286
2gb_ddr_mobile_sdram_t69m.pdf - Rev. M 11/10 EN
48
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2009 Micron Technology, Inc. All rights reserved.
相關(guān)PDF資料
PDF描述
MT46H256M32L4CM-54IT:A 256M X 32 DDR DRAM, 5 ns, PBGA90
MT46H256M32L4MC-54AT:A 256M X 32 DDR DRAM, 5 ns, PBGA240
MT46H256M32L4MC-54IT:A 256M X 32 DDR DRAM, 5 ns, PBGA240
MT46H256M32LGMC-54AT:A 256M X 32 DDR DRAM, 5 ns, PBGA240
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