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參數(shù)資料
| 型號： | MSM6542-03GS-VK |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO24 |
| 封裝： | 0.430 INCH, PLASTIC, SOP-24 |
| 文件頁數(shù)： | 46/54頁 |
| 文件大?。?/td> | 406K |
| 代理商： | MSM6542-03GS-VK |
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Semiconductor
MSM6542-010/2/03
117
[Basic check at the early stage of development]
(a) Read/write check
Only the BANK 1/0 bit can be subject to read and write operations without a paritcular
procedure.
The interface can be checked by reading and writing the BANK 1/0 bit.
Check D3 = 0
Read CF register
CF
(0, 0, 0, 0)
R - S1
(1, 1, 1, 1)
*1
*2
*3
Check D3 = 1
CF
(1, 0, 0, 0)
A - S1
(0, 1, 1, 1)
Read CF register
(b) Checking oscillation using software
Oscillator operation can be checked using software through increment of clock registers,
change of the IRQ FLAG
1 and IRQ FLAG2 bits, 30-s adjustment, change of the read flag, and
setting the DP bit at 0. These methods, except setting the DP bit at 0, affect the REST and
STOP bits. Therefore, the method involved in the DP is used in the following flowcharts:
CF register
BANK 1/0
1
CE' register
DP
1
Read CE' register
DP
1
Y
N
*1
*2
1
*1
(D3, D2, D1, D0)
*2
Use addresses and data having values opposite
to those in *1 above to charge or discharge the
bus in the reverse phase.
*3
D3 is the BANK 1/0 bit.
*4
Same idea as *2
*1, *2
The DP bit is not set at 1 for 62
s after it
changes from 1 to 0. When the step marked
*2 is executed within the 62
s interval but
oscillation is in progress, the loop marked
*1 is completed within 62
s.
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