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參數(shù)資料
| 型號： | MSM6542-03GS-VK |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO24 |
| 封裝： | 0.430 INCH, PLASTIC, SOP-24 |
| 文件頁數(shù)： | 20/54頁 |
| 文件大?。?/td> | 406K |
| 代理商： | MSM6542-03GS-VK |
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Semiconductor
MSM6542-01/02/03
94
CY0
Duty cycle of the low level
when IT/PLS1 = 0
0
1
CY2
CY1
1/2
1/8192
1/491520
1/4915200
0
1
0
1
0
1
0
1
0
1
0
1
Period
1/1024 s
1/128 s
1/64 s
1/16 s
1/2 s
1 s
1 min
10 min
C
E’ Register (Control E' Register)
a)
DP (D
0) (Data Protect bit)
This bit has the following two functions:
i)
Restricts write operation to the IC.
ii)
Prolongs the resetting of the IRQ FLAG
1 bit when the bit is read within 122 s
of occurrence of a periodic alarm in the periodic interrupt mode. Also prolongs
the resetting the IRQ FLAG
2 bit in the same way in the alarm interrupt mode.
i)
Restriction of write operation
When the DP bit is 0, normal write operation is enabled. When the bit is 1, however,
the IC is write-protected except the BANK 1/0 (D
3) bit of the CF register for which
write operation is always allowed.
The DP bit is designed to protect the registers from extenal noise, particularly
erroneous write signal noise which is generated when the standby power supply
voltage is switched to the system power supply voltage or vice versa. After the
necessary data is written, it is recommended that the DP bit be set at 1 if only read
operation is performed.
ii)
Prolongation of reset of the IRQ FLAG bits
When the IT/PLS
1 (D2) bit of the CD register is 1 (periodic interrupt mode) with the DP
bit set at 0, reading the C
E register clears the IRQ FLAG1 bit. This is also true for the
IT/PLS
2 (D3) bit when it is 1 (alarm interrupt mode): reading CE register clears the IRQ
FLAG
2 bit.
When the IRQ FLAG
1 bit is read within about 122 s of occurrence of an interrupt with
the IT/PLS
1 (D2) bit of the CD register set at 1 (periodic interrupt mode), the IRQ FLAG1
bit is not cleared immediately. Similarly, the IRQ FLAG
2 bit is not cleared immediately
when the IT/PLS
2 (D3) bit is 1 (alarm interrupt mode).
These IRQ FLAG bits are
cleared about 122
s after an interrupt occurs. When these bits are read at least about
122
s after an interrupt occurs, they are cleared immediately. For more information,
see the description of "C
E REGISTER."
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