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參數(shù)資料
| 型號： | MSM6542-03GS-VK |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 時鐘/數(shù)據(jù)恢復及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO24 |
| 封裝： | 0.430 INCH, PLASTIC, SOP-24 |
| 文件頁數(shù)： | 31/54頁 |
| 文件大?。?/td> | 406K |
| 代理商： | MSM6542-03GS-VK |
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Semiconductor
MSM6542-01/02/03
104
Use of CS
1
V
IH and VIL of CS1 has the following three functions:
1.
Validate the interface with the microcomputer when 5V power is used.
2.
Inhibit use of the control bus, data bus, and address bus and prevent through-current
specific to CMOS input in the standby mode.
3.
Protect register data of the IC when the standby mode is entered or exited.
To implement these functions:
1.
To validate the interface with the microcomputer when 5V power is used, input must be
at least 4/5 VDD.
2.
When the mode is switched to the standby mode, input must be 1/5 V
DD or less to inhibit
use of the buses. In the standby mode, input must be nearly 0V to prevent through-current.
3.
When the standby mode is entered or exited, the main power and CS
1 must conform the
following timing charts:
Note:
In the standby mode, the operating power supply voltage is from 4V to 2V (minimum
value). Clocking is performed but the interface to the outside of the IC is not assured.
When a system is implemented with DP = 0:
Exiting from the standby mode
4 ~ 6V
4 ~ 4.5V*
1s(MIN)
Main power
supply (5V)
4 ~ 4.5V*
CS1
Switching to the standby mode
POWER OFF
4
5 VDD
1
5 VDD (VDD for the IC described in
this data sheet is 2 to 6 V.)
During the period,
CS0 of the IC
is high or
WR is not generated.
4 to 4.5V* are measures of the minimum 5-V
main power supply voltage at which the CPU
does not assure correct program operations.
This is also the for the following timing chart:
The purpose is to maintain data in
static RAM in the standby mode.
0V
On and after this period, the interface
through the IC is possible
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