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參數(shù)資料
| 型號(hào)： | MSC8256TVT800B |
| 廠(chǎng)商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | 0-BIT, OTHER DSP, PBGA783 |
| 封裝： | 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783 |
| 文件頁(yè)數(shù)： | 55/68頁(yè) |
| 文件大小： | 910K |
| 代理商： | MSC8256TVT800B |
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Hardware Design Considerations
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 3
Freescale Semiconductor
59
3.5.1
DDR Memory Related Pins
This section discusses the various scenarios that can be used with either of the MSC8256 DDR ports.
Note:
The signal names in Table 40, Table 41 and Table 42 are generic names for a DDR SDRAM interface. For actual pin
names refer to Table 1.
3.5.1.1
DDR Interface Is Not Used
Table 40. Connectivity of DDR Related Pins When the DDR Interface Is Not Used
Signal Name
Pin Connection
MDQ[0–63]
NC
MDQS[7–0]
NC
MDQS[7–0]
NC
MA[15–0]
NC
MCK[0–2]
NC
MCK[0–2]
NC
MCS[1–0]
NC
MDM[7–0]
NC
MBA[2–0]
NC
MCAS
NC
MCKE[1–0]
NC
MODT[1–0]
NC
MMDIC[1–0]
NC
MRAS
NC
MWE
NC
MECC[7–0]
NC
MDM8
NC
MDQS8
NC
MDQS8
NC
MAPAR_OUT
NC
MAPAR_IN
NC
MVREF3
NC
GVDD1/GVDD23
NC
Notes:
1.
For the signals listed in this table, the initial M stands for M1 or M2 depending on which DDR controller is not used.
2.
If the DDR controller is not used, disable the internal DDR clock by setting the appropriate bit in the System Clock Control
Register (SCCR) and put all DDR I/O in sleep mode by setting DRx_GCR[DDRx_DOZE] (for DDR controller x). See the
Clocks and General Configuration Registers chapters in the MSC8256 Reference Manual for details.
3.
For MSC8256 Revision 1 silicon, these pins were connected to GND. For newer revisions of the MSC8256, connecting these
pins to GND increases device power consumption.
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