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| 型號： | MSC8256TVT800B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, OTHER DSP, PBGA783 |
| 封裝： | 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 43/68頁 |
| 文件大?。?/td> | 910K |
| 代理商： | MSC8256TVT800B |
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MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 3
Electrical Characteristics
Freescale Semiconductor
48
2.6.5.2
RGMII AC Timing Specifications
Table 34 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.
Table 35 presents the RGMII AC timing specification for applications required non-delayed clock on board.
Figure 25 shows the RGMII AC timing and multiplexing diagrams.
Table 34. RGMII at 1 GHz2 with On-Board Delay3 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)4
tSKEWT
–-0.5
—
0.5
ns
Data to clock input skew (at receiver) 4
tSKEWR
1—
2.6
ns
Notes:
1.
At recommended operating conditions with VDDIO of 2.5 V ± 5%.
2.
RGMII at 100 MHz support is guaranteed by design.
3.
Program GCR4 as 0x00000000.
4.
This implies that PC board design requires clocks to be routed such that an additional trace delay of greater than 1.5 ns and
less than 2.0 ns is added to the associated clock signal.
Table 35. RGMII at 1 GHz2 with No On-Board Delay3 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)4
tSKEWT
–2.6
—
–1.0
ns
Data to clock input skew (at receiver)4
tSKEWR
–0.5
—
0.5
ns
Notes:
1.
At recommended operating conditions with VDDIO of 2.5 V ± 5%.
2.
RGMII at 100 MHz support is guaranteed by design.
3.
GCR4 should be programmed as 0x000CC330.
4.
This implies that PC board design requires clocks to be routed with no additional trace delay
Figure 25. RGMII AC Timing and Multiplexing
GTX_CLK
tSKEWT
TX_CTL
txd[7:4]
txd[3:0]
(At transmitter)
TXD[3:0]
RX_CTL
rxd[8:5]
rxd[3:0]
RXD[3:0]
RX_CLK
(At Receiver)
tSKEWR
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