參數(shù)資料
型號: MSC8256TVT800B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 0-BIT, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783
文件頁數(shù): 53/68頁
文件大小: 910K
代理商: MSC8256TVT800B
Hardware Design Considerations
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 3
Freescale Semiconductor
57
3.3
Clock and Timing Signal Board Layout Considerations
When laying out the system board, use the following guidelines:
Keep clock and timing signal paths as short as possible and route with 50
Ω impedance.
Use a serial termination resistor placed close to the clock buffer to minimize signal reflection. Use the following
equation to compute the resistor value:
Rterm = Rim – Rbuf
where Rim = trace characteristic impedance
Rbuf = clock buffer internal impedance.
3.4
SGMII AC-Coupled Serial Link Connection Example
Figure 39 shows an example of a 4-wire AC-coupled serial link connection. For additional layout suggestions, see AN3556
MSC815x High Speed Serial Interface Hardware Design Considerations, available on the Freescale website or from your local
sales office or representative.
Figure 39. 4-Wire AC-Coupled SGMII Serial Link Connection Example
SGMII
SerDes Interface
50
Ω
50
Ω
Transmitter
SR[1–2]_TX[[1–2]
SR[1–2]_RX[1–2]
SR[1–2]_TX[1–2]
SR[1–2]_RX[1–2]
Receiver
CTX
50
Ω
50
Ω
SR[1–2]_RX[1–2]
SR[1–2]_RX[1–2]]
Receiver
Transmitter
SR[1–2]_TX[1–2
]
SR[1–2]_TX[1–2]
CTX
50
Ω
50
Ω
50
Ω
50
Ω
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