參數(shù)資料
型號(hào)： MSC8256TVT800B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 0-BIT, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783
文件頁(yè)數(shù)： 31/68頁(yè)
文件大?。?/td> 910K
代理商： MSC8256TVT800B
Electrical Characteristics
MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 3
Freescale Semiconductor
37
Figure 11 shows the DDR2 and DDR3 SDRAM interface input timing diagram.
2.6.1.2
DDR SDRAM Output AC Timing Specifications
Table 21 provides the output AC timing specifications for the DDR SDRAM interface.
Figure 11. DDR2 and DDR3 SDRAM Interface Input Timing Diagram
Table 21. DDR SDRAM Output AC Timing Specifications
Parameter
Symbol 1
Min
Max
Unit
Notes
MCK[n] cycle time
tMCK
2.5
5
ns
2
ADDR/CMD output setup with respect to MCK
800 MHz data rate
667 MHz data rate
tDDKHAS
0.917
1.10
—
ns
3
ADDR/CMD output hold with respect to MCK
800 MHz data rate
667 MHz data rate
tDDKHAX
0.767
1.02
—
ns
3
MCSn output setup with respect to MCK
800 MHz data rate
667 MHz data rate
tDDKHCS
0.917
1.10
—
ns
3
MCSn output hold with respect to MCK
800 MHz data rate
667 MHz data rate
tDDKHCX
0.767
1.02
—
ns
3
MCK to MDQS Skew
800 MHz data rate
667 MHz data rate
tDDKHMH
–0.4
–0.6
0.375
0.6
ns
4
MDQ/MECC/MDM output setup with respect to MDQS
800 MHz
667 MHz
tDDKHDS,
tDDKLDS
300
375
—
ps
5
MDQ/MECC/MDM output hold with respect to MDQS
800 MHz
667 MHz
tDDKHDX,
tDDKLDX
300
375
—
ps
5
MDQS preamble
tDDKHMP
–0.9
× tMCK
—ns
—
MDQS postamble
tDDKHME
–0.4
× tMCK
–0.6
× tMCK
ns
—
MCK[n]
tMCK
MDQ[n]
MDQS[n]
tDISKEW
D1
D0
tDISKEW
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