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參數(shù)資料
| 型號： | MSC8256TVT800B |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 0-BIT, OTHER DSP, PBGA783 |
| 封裝： | 29 X 29 MM, LEAD FREE, PLASTIC, FCBGA-783 |
| 文件頁數(shù)： | 15/68頁 |
| 文件大?。?/td> | 910K |
| 代理商： | MSC8256TVT800B |
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MSC8256 Six-Core Digital Signal Processor Data Sheet, Rev. 3
Freescale Semiconductor
22
AH17
M1DQS6
I/O
GVDD1
AH18
I/O
GVDD1
AH19
M1DQ48
I/O
GVDD1
AH20
M1DQ49
I/O
GVDD1
AH21
VSS
Ground
N/A
AH22
TDM0RCK/GE2_RD23
I/O
NVDD
AH23
TDM0RDT/GE2_RD33
I/O
NVDD
AH24
TDM0TSN/GE2_RD03
I/O
NVDD
AH25
TDM1RCK/GE2_RD13
I/O
NVDD
AH26
TDM3TDT/GE1_RD33
I/O
NVDD
AH27
TDM3TCK/GE1_RD23
INVDD
AH28
VSS
Ground
N/A
Notes:
1.
Reserved signals should be disconnected for compatibility with future revisions of the device. Non-user signals are reserved
for manufacturing and test purposes only. The assigned signal name is used to indicate whether the signal must be
unconnected (Reserved), pulled down (VSS), or pulled up (VDD).
2.
Signal function during power-on reset is determined by the RCW source type.
3.
Selection of TDM versus RGMII functionality is determined by the RCW bit values.
4.
Selection of RapidIO, SGMII, and PCI Express functionality is determined by the RCW bit values.
5.
Selection of the GPIO function and other functions is done by GPIO register setup. For configuration details, see the GPIO
chapter in the MSC8256 Reference Manual.
6.
Open-drain signal.
7.
Internal 20 K
Ω pull-up resistor.
8.
For signals with GPIO functionality, the open-drain and internal 20 K
Ω pull-up resistor can be configured by GPIO register
programming. See the GPIO chapter of the MSC8256 Reference Manual for configuration details.
9.
Connect to power supply via external filter. See Section 3.2, PLL Power Supply Design Considerations for details.
10. Pin types are: Ground = all VSS connections; Power = all VDD connections; I = Input; O = Output; I/O = Input/Output; NC =
not connected.
Table 1. Signal List by Ball Number (continued)
Ball Number
Signal Name1,2
Pin Type10
Power Rail
Name
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