參數(shù)資料
型號： MSC8144VT800B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 133 MHz, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù)： 77/80頁
文件大?。?/td> 1250K
代理商： MSC8144VT800B
Revision History
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
79
7
Dec 2007
Changed minimum voltage level for VDDM3 to 1.213 (1.25 – 3%) in Table 3.
Added POS to titles in Section 2.6.6.
Added additional signals to titles in Section 2.6.8. Added high and low voltage ranges to Table 19.
Added ATM and POS to headings in Section 2.7.11. Changed characteristics to generic input/output in Table 52,
Figure 33, and Figure 34.
Replaced Sections 2.7.13 and 2.7.14 with new Section 2.7.13, Asynchronous Signal Timing. Renumbered
subsequent sections, tables, and figures.
Added POS to all UTOPIA references in Section 3.4.5.
8
Dec 2007
Changed GCR4 program value to 0x0004C130 in Note 7 in Table 51.
9
Mar 2008
Changed description of Table 20 in Section 2.7.2.
10
Apr 2008
Added 3 to the PLL supply voltage row in Table 2.
Changed the first sentence in Section 3.4.8 to reflect that Table 70 indicates what to do with pins if they are
“not” required by the design. Changed the Pin Connection for GPIO[0–31] to GND.
Updated ordering information in Section 4.
Multiple corrections of minor punctuation errors.
11
Aug 2008
Removed the comment about preliminary estimates before Table 4 and removed non-DDR rows in the table.
Table 9 and Table 11 for DDR and DDR2 SDRAM capacitance removed and subsequent tables renumbered.
Changed units for IOH and IOL to mA in Table 9.
Removed signal low and high input current from Table 12.
Added a note to Table 15 to exclude TDM and TMS. Removed reference to overshoot and undershoot and
associated figure.
Changed minimum clock frequency to 33 MHz and maximum clock frequency to 133 MHz in Table 16.
Deleted old Table 17 Clock Parameters.
Changed minimum input clock frequency to 33 MHz in Table 19.
Changed the tDDKHAX minimum value in Table 23 to 1.85 ns.
Removed tREFPJ and tREFCJ from Table 24 because the specifications are not required or tested.
Removed tPCRSTCLK, tPCRSTOFF, tPCRST, and tPCRHFA from Table 36 because the specifications are not required
or tested.
Removed tUAVKH and tUAVXH from Table 38 because the specifications are not required or tested.
The parameters tMDCH, tMDCR, and tMDHF were removed from Table 40 because the specifications are not
required or tested.
The parameters tMTXH/tMTX, tMTXR, and tMTXF were removed from Table 41 because the specifications are not
required or tested.
The parameters tMRXH/tMRX, tMRXR, and tMRXF were removed from Table 42 because the specifications are not
required or tested.
The parameters tRMXH/tRMX, tRMXR, and tRMXF were removed from Table 43 because the specifications are not
required or tested.
Removed the parameters tRGT, tRGTH/tRGT (1000Base-T), tRGTH/tRGT (10Base-T), tRGTR, tRGTF, tG12, and
tG125H/tG125 were removed from Table 45 and Table 46 because the specifications are not required or tested.
Changed tUEKHOX to guaranteed by design in Table 47.
Updated Figure 35 and Figure 36 SPI timing diagrams.
Removed TCK rise and fall time from Table 50.
Updated orderable part numbers in Section 4.
12
Aug 2008
Changed b8t to bit in the M3 memory description on the first page.
Changed maximum input high voltage (VIH) for SPI to 3.465 in the first row of Table 14.
Changed packet processor to QUICC Engine Subsystem in the last row of Table 18.
13
Feb 2009
In Figure 31, for GTX_CLK, changed (at transmitter) to (at DSP) and for RX_CLK, changed (at PHY) to (at
DSP).
Updated package drawing to the latest revision, Case No. 1842-04 in Figure 44.
14
Jul 2009
Updated MVREF equations and temperature ranges in Table 3.
Updated orderable part numbers to Section 4.
15
Nov 2009
Updated Core and PLL input voltage tolerance in Table 3.
16
May 2010
Corrected typo in Table 23. Changed MCLK minimum time to 5 ns.
Table 66. Document Revision History (continued)
Rev.
Date
Description
相關(guān)PDF資料
PDF描述
MSC8144SVT1000A 133 MHz, OTHER DSP, PBGA783
MSC8144TVT1000A 133 MHz, OTHER DSP, PBGA783
MSC8144SVT1000B 133 MHz, OTHER DSP, PBGA783
MSC8144VT1000A 133 MHz, OTHER DSP, PBGA783
MSC8144SVT800A 133 MHz, OTHER DSP, PBGA783
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSC81450M 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:RF & MICROWAVE TRANSISTORS AVIONICS APPLICATIONS
MSC8151 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Single-Core Digital Signal Processor
MSC8151SAG1000B 制造商:Freescale Semiconductor 功能描述:STARCORE DSP, 1X 1GHZ SC3850 CORES, MAPLE-B ACCELERATOR, DDR - Bulk 制造商:Freescale Semiconductor 功能描述:STARCORE DSP, 1X 1GHZ SC3850 CORES, MAPLE-B ACCELERATOR, DDR - Trays 制造商:Freescale Semiconductor 功能描述:IC DSP 1X 1GHZ SC3850 783FCBGA
MSC8151SVT1000B 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Darwin RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
MSC8151TVT1000B 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Darwin RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
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