參數(shù)資料
型號(hào)： MSC8144VT800B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號(hào)處理
英文描述： 133 MHz, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù)： 61/80頁
文件大?。?/td> 1250K
代理商： MSC8144VT800B
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
64
Figure 40 shows the test access port timing diagram
Figure 41 shows the TRST timing diagram.
3
Hardware Design Considerations
The following sections discuss areas to consider when the MSC8144 device is designed into a system.
3.1
3.1.1
Power-on Sequence
Use the following guidelines for power-on sequencing:
There are no dependencies in power-on/power-off sequence between VDDM3 and VDD supplies.
There are no dependencies in power-on/power-off sequence between RapidIO supplies: VDDSXC, VDDSXP,
VDDRIOPLL and other MSC8144 supplies.
VDDPLL should be coupled with the VDD power rail with extremely low impedance path.
External voltage applied to any input line must not exceed the related to this port I/O supply by more than 0.6 V at any time,
including during power-up. Some designs require pull-up voltages applied to selected input lines during power-up for
configuration purposes. This is an acceptable exception to the rule during start-up. However, each such input can draw up to 80
mA per input pin per MSC8144 device in the system during start-up. An assertion of the inputs to the high voltage level before
power-up should be with slew rate less than 4 V/ns.
Figure 40. Test Access Port Timing
Figure 41. TRST Timing
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
Input Data Valid
Output Data Valid
TMS
tTDIVKH
tTDIXKH
tTDOHOV
tTDOHOZ
TRST
(Input)
tTRST
相關(guān)PDF資料
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