參數(shù)資料
型號: MSC8144VT800B
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 133 MHz, OTHER DSP, PBGA783
封裝: 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù): 62/80頁
文件大?。?/td> 1250K
代理商: MSC8144VT800B
Hardware Design Considerations
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
65
The following supplies should rise before any other supplies in any sequence
VDD and VDDPLL coupled together
VDDM3
After the above supplies rise to 90% of their nominal value the following I/O supplies may rise in any sequence (see Figure 42):
VDDGE1
VDDGE2
VDDIO
VDDDDR and MVREF coupled one to another. MVREF should be either at same time or after VDDDDR.
VDDM3IO
V25M3
Note:
1.
This recommended power sequencing is different from the MSC8122/MSC8126.
2.
If no pins that require VDDGE1 as a reference supply are used (see Table 1), VDDGE1 can be tied to GND.
3.
If no pins that require VDDGE2 as a reference supply are used (see Table 1), VDDGE2 can be tied to GND.
4.
If the DDR interface is not used, VDDDDR and MVREF can be tied to GND.
5.
If the M3 memory is not used, VDDM3, VDDM3IO, and V25M3 can be tied to GND.
6.
If the RapidIO interface is not used, VDDSX, VDDSXP, and VDDRIOPLL can be tied to GND.
3.1.2
Start-Up Timing
Section 2.6.1 describes the start-up timing.
Figure 42. VDDM3, VDDM3IO and V25M3 Power-on Sequence
VDDM3, VDD, and VDDPLL
90%
I/O supplies
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