參數(shù)資料
型號： MSC8144VT800B
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 133 MHz, OTHER DSP, PBGA783
封裝： 29 X 29 MM, LEAD FREE, PLASTIC, FCPBGA-783
文件頁數(shù)： 22/80頁
文件大?。?/td> 1250K
代理商： MSC8144VT800B
Electrical Characteristics
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
29
This section describes the DC electrical characteristics for the MSC8144.
2.5.1
DDR SDRAM DC Electrical Characteristics
This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8144.
Note:
DDR SDRAM uses VDDDDR(typ) = 2.5 V and DDR2 SDRAM uses VDDDDR(typ) = 1.8 V.
2.5.1.1
DDR2 (1.8 V) SDRAM DC Electrical Characteristics
Table 6 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MSC8144 when
VDDDDR(typ) = 1.8 V.
Table 6. DDR2 SDRAM DC Electrical Characteristics for VDDDDR (typ) = 1.8 V
Parameter/Condition
Symbol
Min
Max
Unit
I/O supply voltage1
VDDDDR
1.7
1.9
V
I/O reference voltage2
MVREF
0.49
× VDDDDR
0.51
× VDDDDR
V
I/O termination voltage3
VTT
MVREF –0.04
MVREF + 0.04
V
Input high voltage
VIH
MVREF + 0.125
VDDDDR +0.3
V
Input low voltage
VIL
–0.3
MVREF – 0.125
V
Output leakage current4
IOZ
–50
50
μA
Output high current (VOUT = 1.420 V)
IOH
–13.4
—
mA
Output low current (VOUT = 0.280 V)
IOL
13.4
—
mA
Notes:
1.
VDDDDR is expected to be within 50 mV of the DRAM VDD at all times.
2.
MVREF is expected to be equal to 0.5 × VDDDDR, and to track VDDDDR DC variations as measured at the receiver.
Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.
3.
VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of VDDDDR.
4.
Output leakage is measured with all outputs are disabled, 0 V
≤ V
OUT
≤ V
DDDDR.
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