![](http://datasheet.mmic.net.cn/100000/IF180C52TXXX-20R_datasheet_3493957/IF180C52TXXX-20R_822.png)
822
32099I–01/2012
AT32UC3L016/32/64
Fix/Workaround
Solution 1: Make sure that the appropriate instructions are executed from RAM, and that a
waiting-loop is executed from RAM waiting 500ns or more before executing from flash.
Solution 2. Execute from flash with a clock with period longer than 500ns. This guarantees
that no new read access is attempted before the flash has had time to settle in the new read
mode.
4.
Flash self programming may fail in one wait state mode
Writes in flash and user pages may fail if executing code is located in address space
mapped to flash, and the flash controller is configured in one wait state mode (the Flash
Wait State bit in the Flash Control Register (FCR.FWS) is one).
Fix/Workaround
Solution 1: Configure the flash controller in zero wait state mode (FCR.FWS=0).
Solution 2: Configure the HMATRIX master 1 (CPU Instruction) to use the unlimited burst
length transfer mode (MCFG1.ULBT=0), and the HMATRIX slave 0 (FLASHCDW) to use
the maximum slot cycle limit (SCFG0.SLOT_CYCLE=255).
5.
VERSION register reads 0x100
The VERSION register reads 0x100 instead of 0x102.
Fix/Workaround
None.
35.4.4
SAU
1.
The SR.IDLE bit reads as zero
The IDLE bit in the Status Register (SR.IDLE) reads as zero.
Fix/Workaround
None.
2.
Open Mode is not functional
The Open Mode is not functional.
Fix/Workaround
None.
3.
VERSION register reads 0x100
The VERSION register reads 0x100 instead of 0x110.
Fix/Workaround
None.
35.4.5
HMATRIX
1.
In the PRAS and PRBS registers, the MxPR fields are only two bits
In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits.
The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
35.4.6
Power Manager
1.
CONFIG register reads 0x4F
The CONFIG register reads 0x4F instead of 0x43.
Fix/Workaround
None.