![](http://datasheet.mmic.net.cn/100000/IF180C52TXXX-20R_datasheet_3493957/IF180C52TXXX-20R_368.png)
368
32099I–01/2012
AT32UC3L016/32/64
19.6.3
Synchronous and Asynchronous Modes
19.6.3.1
Transmitter Operations
The transmitter performs equally in both synchronous and asynchronous operating modes
(MR.SYNC). One start bit, up to 9 data bits, an optional parity bit, and up to two stop bits are
successively shifted out on the TXD pin at each falling edge of the serial clock. The number of
data bits is selected by the Character Length field (MR.CHRL) and the MR.MODE9 bit. Nine bits
are selected by writing a one to MODE9, overriding any value in CHRL. The parity bit configura-
tion is selected in the MR.PAR field. The Most Significant Bit First bit (MR.MSBF) selects which
data bit to send first. The number of stop bits is selected by the MR.NBSTOP field. The 1.5 stop
bit configuration is only supported in asynchronous mode.
Figure 19-4. Character Transmit
The characters are sent by writing to the Character to be Transmitted field (THR.TXCHR). The
transmitter reports status with the Transmitter Ready (TXRDY) and Transmitter Empty
(TXEMPTY) bits in the Channel Status Register (CSR). TXRDY is set when THR is empty.
TXEMPTY is set when both THR and the transmit shift register are empty (transmission com-
plete). Both TXRDY and TXEMPTY are cleared when the transmitter is disabled. Writing a
character to THR while TXRDY is zero has no effect and the written character will be lost.
Figure 19-5. Transmitter Status
19.6.3.2
Asynchronous Receiver
If the USART is configured in an asynchronous operating mode (MR.SYNC = 0), the receiver will
oversample the RXD input line by either 8 or 16 times the baud rate clock, as selected by the
Oversampling Mode bit (MR.OVER). If the line is zero for half a bit period (four or eight consecu-
tive samples, respectively), a start bit will be assumed, and the following 8th or 16th sample will
determine the logical value on the line, in effect resulting in bit values being determined at the
middle of the bit period.
D0
D1
D2
D3
D4
D5
D6
D7
TXD
Start
Bit
Parity
Bit
Stop
Bit
Example: 8-bit, Parity Enabled One Stop
Baud Rate
Clock
D0
D1
D2
D3
D4
D5
D6
D7
TXD
Start
Bit
Parity
Bit
Stop
Bit
Baud Rate
Clock
Start
Bit
Write
THR
D0
D1
D2
D3
D4
D5
D6
D7
Parity
Bit
Stop
Bit
TXRDY
TXEMPTY