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Depending on the reset source, when a reset occurs, some parts of the device are not always
reset. Only the Power-on Reset (POR) will force a whole device reset. Refer to the table in the
Module Configuration section at the end of this chapter for further details. The latest reset cause
can be read in the RCAUSE register, and can be read during the applications boot sequence in
order to determine proper action.
12.6.6.1
Power-on Reset Detector
The Power-on Reset 1.8V (POR18) detector monitors the VDDCORE supply pin and generates
a Power-on Reset (POR) when the device is powered on. The POR is active until the
VDDCORE voltage is above the power-on threshold level (V
POT). The POR will be re-generated
if the voltage drops below the power-on threshold level. See Electrical Characteristics for para-
metric details.
The Power-on Reset 3.3V (POR33) detector monitors the internal regulator supply pin and gen-
erates a Power-on Reset (POR) when the device is powered on. The POR is active until the
internal regulator supply voltage is above the regulator power-on threshold level (V
POT). The
POR will be re-generated if the voltage drops below the regulator power-on threshold level. See
Electrical Characteristics for parametric details.
12.6.6.2
External Reset
The external reset detector monitors the RESET_N pin state. By default, a low level on this pin
will generate a reset.
12.6.7
Clock Failure Detector
This mechanism automatically switches the main clock source to the safe RCSYS clock when
the main clock source fails. This may happen when an external crystal is selected as a source
for the main clock and the crystal is not mounted on the board. The main clock is compared with
RCSYS, and if no rising edge of the main clock is detected during one RCSYS period, the clock
is considered to have failed.
The detector is enabled by writing a one to the Clock Failure Detection Enable bit in the Clock
Failure Detector Control Register (CFDCTRL.CFDEN). As soon as the detector is enabled, the
clock failure detector will monitor the divided main clock. Note that the detector does not monitor
the main clock if RCSYS is the source of the main clock, or if the main clock is temporarily not
available (startup-time after a wake-up, switching timing etc.), or in sleep mode where the main
clock is driven by the RCSYS (Stop and DeepStop mode). When a clock failure is detected, the
main clock automatically switches to the RCSYS clock and the Clock Failure Detected (CFD)
interrupt is generated if enabled. The MCCTRL register is also changed by hardware to indicate
that the main clock comes from RCSYS.
12.6.8
Interrupts
The PM has a number of interrupt sources:
AE - Access Error,
SM33 Reset
Internal regulator supply voltage below the SM33 threshold
voltage. This generates a Power-on Reset.
Watchdog Timer
See Watchdog Timer documentation
OCD
See On-Chip Debug documentation
Reset Source
Description