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型號(hào)：	MQ80C52CXXX-12/883:R
廠商：	TEMIC SEMICONDUCTORS
元件分類：	微控制器/微處理器
英文描述：	8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù)：	102/849頁(yè)
文件大?。?/td>	12530K

32099I–01/2012

AT32UC3L016/32/64

Internal synchronization

Due to multiple clock domains in the DFLLIF, values in the DFLLIF configuration registers need

to be synchronized to other clock domains. The status of this synchronization can be read from

the Power and Clocks Status Register (PCLKSR). Before writing to a DFLLIF configuration reg-

ister, the user must check that the DFLLn Synchronization Ready bit (DFLLnRDY) in PCLKSR is

set. When this bit is set, the DFLL can be configured, and CLK_DFLL is ready to be used. Any

write to a DFLLIF configuration register while DFLLnRDY is cleared will be ignored.

Before reading the value in any of the DFLL configuration registers a one must be written to the

Synchronization bit (SYNC) in the DFLLn Synchronization Register (DFLLnSYNC). The DFLL

configuration registers are ready to be read when PCLKSR.DFLLnRDY is set.

Disabling the DFLL

The DFLL is disabled by writing a zero to DFLLnCONF.EN. No other bits or fields in DFLLn-

CONF must be changed simultaneously.

After disabling the DFLL, PCLKSR.DFLLnRDY will not be set. It is not required to wait for

PCLKSR.DFLLnRDY to be set before re-enabling the DFLL.

Open loop operation

After enabling the DFLL, open loop mode is selected by writing a zero to the Mode Selection bit

(MODE) in DFLLnCONF. When operating in open loop mode the output frequency of the DFLL

will be determined by the values written to the Coarse Calibration Value field (COARSE) and the

Fine Calibration Value field (FINE) in the DFLLnCONF register. When writing to COARSE and

FINE, be aware that the output frequency must not exceed the maximum frequency of the

device after the division in the clock generator. It is possible to change the value of COARSE

and FINE, and thereby the output frequency of the DFLL, while the DFLL is enabled and in use.

The DFLL clock is ready to be used when PCLKSR.DFLLnRDY is cleared after enabling the

The frequency range in open loop mode is 40-150MHz, but maximum frequency can be higher,

and the minimum frequency can be lower. The best way to start the DFLL at a specific frequency

in open loop mode is to first configure it for closed loop mode, see Section 13.5.3.5. When a lock

is achieved, read back the COARSE and FINE values and switch to open loop mode using these

values. An alternative approach is to use the Frequency Meter (FREQM) to monitor the DFLL

frequency and adjust the COARSE and FINE values based on measurement results form the

FREQM. Please refer to the FREQM chapter for more information on how to use it. Note that the

output frequency of the DFLL will drift when in open loop mode due to temperature and voltage

changes. Please refer to the Electrical Characteristics chapter for details.

Closed loop operation

The DFLL must be correctly configured before closed loop operation can be enabled. After

en ab ling the DF LL , e n a b le an d select a r e fer e n c e clock (CLK_ D FL LIF _ REF ) .

CLK_DFLLIF_REF is a generic clock, please refer to Generic Clocks section for details. Then

set the maximum step size allowed in finding the COARSE and FINE values by setting the

Coarse Maximum Step field (CSTEP) and Fine Maximum Step field (FSTEP) in the DFLLn Max-

imum Step Register (DFLLnSTEP). A small step size will ensure low overshoot on the output

frequency, but can typically result in longer lock times. A high value might give a big overshoot,

but can typically give faster locking. DFLLnSTEP.CSTEP and DFLLnSTEP.FSTEP must be

lower than 50% of the maximum value of DFLLnCONF.COARSE and DFLLnCONF.FINE

respectively. Then select the multiplication factor in the Integer Multiply Factor field (IMUL) and

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