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參數(shù)資料
| 型號： | MPC97R73FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | LQFP-52 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 252K |
| 代理商： | MPC97R73FA |
MPC97R73
TIMING SOLUTIONS
15
MOTOROLA
Figure 15. Output–to–output Skew tSK(O)
Figure 16. Propagation delay (t(
), static phase
offset) test reference
Figure 17. Output Duty Cycle (DC)
The pin–to–pin skew is defined as the worst case difference
in propagation delay between any similar delay path within a
single device
The time from the PLL controlled edge to the non controlled
edge, divided by the time between PLL controlled edges,
expressed as a percentage
VCC
VCCB2
GND
VCC
VCCB2
GND
tSK(O)
VCC
VCCB2
GND
tP
T0
DC = tP/T0 x 100%
VCC
VCCB2
GND
VCC
VCCB2
GND
t(
)
CCLKx
FB_IN
TJIT(
) = |T0–T1mean|
CCLKx
FB_IN
The deviation in t0 for a controlled edge with respect to a t0 mean in a
random sample of cycles
Figure 18. I/O Jitter
Figure 19. Cycle–to–cycle Jitter
Figure 20. Period Jitter
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs
The deviation in cycle time of a signal with respect to the ideal period over
a random sample of cycles
TN
TJIT(CC) = |TN–TN+1|
TN+1
TJIT(PER) = |TN–1/f0|
T0
tF
tR
VCC=3.3V
VCC=2.5V
2.4
1.8V
0.55
0.6V
Figure 21. Output Transition Time Test Reference
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