參數(shù)資料
型號(hào)： MPC97R73FA
廠商： MOTOROLA INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52
封裝： LQFP-52
文件頁數(shù)： 17/20頁
文件大?。?/td> 252K
代理商： MPC97R73FA
MPC97R73
MOTOROLA
TIMING SOLUTIONS
6
Table 10: AC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = 0°C to 85°C)a b
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input reference frequency
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷24 feedback
÷32 feedback
Input reference frequency in PLL bypass modec
50.0
33.3
25.0
20.0
16.6
12.5
8.33
6.25
120.0
80.0
60.0
48.0
40.0
30.0
20.0
15
TBD
MHz
PLL locked
PLL bypass
fVCO
VCO frequency ranged
200
480
MHz
fMAX
Output Frequency
÷2 output
÷4 output
÷6 output
÷8 output
÷10 output
÷12 output
÷16 output
÷20 output
÷24 output
100.0
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
240.0
120.0
80.0
60.0
48.0
40.0
30.0
24.0
20.0
MHz
PLL locked
fSTOP_CLK
Serial interface clock frequency
20
MHz
VPP
Peak–to–peak Input Voltage
PCLK, PCLK
500
1000
mV
LVPECL
VCMRe
Common Mode Range
PCLK, PCLK
1.2
VCC–0.9
V
LVPECL
frefDC
Reference Input Duty Cycle
40
60
%
tr, tf
CCLKx Input Rise/Fall Time
1.0
ns
0.8 to 2.0V
t(
)
Propagation Delay (static phase offset)
CCLKx to FB_IN
PCLK to FB_IN
±150
ps
PLL locked
tsk(O)
Output-to-output Skewf
300
ps
DC
Output duty cycle
45
50
55
%
tr, tf
Output Rise/Fall Time
0.1
1.0
ns
0.55 to 2.4V
tPLZ, HZ
Output Disable Time
8
ns
tPZL, LZ
Output Enable Time
8
ns
tJIT(CC)
Cycle-to-cycle jitter
RMS (1
σ)g
TBD
ps
tJIT(PER)
Period Jitter
RMS (1
σ)
TBD
ps
tJIT(
)
I/O Phase Jitter
RMS (1
σ)
TBD
ps
BW
PLL closed loop bandwidthh
kHz
tLOCK
Maximum PLL Lock Time
10
ms
a
All AC characteristics are design targets and subject to change upon device characterization.
b
AC characteristics apply for parallel output termination of 50
to VTT.
c
In bypass mode, the MPC97R73 divides the input reference clock.
d
The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = fVCO ÷ (M VCO_SEL)
eVCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range
and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts static phase offset t(
).
f
See application section for part-to-part skew calculation.
g
See application section for a jitter calculation for other confidence factors than 1
s.
h
-3 dB point of PLL transfer characteristics.
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