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參數(shù)資料
| 型號(hào)： | MPC9991FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 144K |
| 代理商： | MPC9991FA |
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9991/D
Rev 0, 12/2001
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
288
Product Preview
3.3V Differential ECL/PECL
PLL Clock Generator
The MPC9991 is a 3.3 V compatible, PLL based ECL/PECL clock driv-
er. Using SiGe technology and a fully differential design ensures optimum
skew and PLL jitter performance. The performance of the MPC9991
makes the device ideal for workstation, mainframe computer and tele-
communication applications. With output frequencies up to 400 MHz and
output skews less than 150 ps1 the device meets the needs of the most
demanding clock applications. The MPC9991 offers a differential ECL/
PECL input for applications which need to lock to an existing clock signal.
It also offers a secondary single–ended ECL/PECL clock for system test
capabilities.
Features
13 differential outputs, PLL based clock generator
SiGe technology supports minimum output skew (max. 150 ps1)
Supports up to three individual generated output clock frequencies with
a maximum clock frequency up to 400 MHz
External PLL feedback supports zero-delay capability
Selectable SYNC pulse generation
ECL/PECL compatible differential clock inputs and outputs
Single 3.3V (PECL) or -3.3V (ECL) supply
Ambient temperature range 0°C to +70°C
Standard 52 lead LQFP package
Pin and function compatible to the MPC991
Functional Description
The MPC9991 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC9991 requires the connection of the differential PLL feedback output QFB to the differential feedback input FB_IN to close
the PLL feedback path. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both
must be selected to match the VCO frequency range. The MPC9991 features frequency programmability between the three
output banks outputs as well as the output to input relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 4:3:1 and
4:3:2 can be realized. The three banks of outputs can each be programmed by the FSEL[3:0] pins of the device. There are 16
different output frequency configurations available in the device. Additionally, the device supports a separate configurable feed-
back output. This allows for the feedback frequency to be programmed independently of the other outputs, providing six input to
output frequency ratios that can be configured by the FSEL_FB[2:0] inputs. The external feedback feature enables the use of the
MPC9991 as a zero-delay buffer. The VCO_SEL pin provides an extended PLL input reference frequency range.
The SYNC pulse generator monitors the phase relationship between the QA[3:] and QC[2:0] output banks. The SYNC genera-
tor output signals the coincident edges of the two output banks. This feature is useful for non binary relationships between output
frequencies (i.e., 3:2 or 4:3 relationships). The SYNC_SEL input switches the QD[1:0] outputs between the SYNC signals and an
extensions to the QC bank of outputs. The REF_SEL pin selects the differential ECL/PECL compatible input pair or a single-en-
ded ECL/PECL compatible input as the reference clock signal. The PLL_EN control selects the PLL bypass configuration for test
and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL.
The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The
MPC9991 requires an external reset signal for start-up and for PLL recovery in the case the external feedback is interrupted. The
MPC9991 is fully 3.3V (PECL) or -3.3V (ECL) compatible and requires no external loop filter components. All inputs accept
PECL/ECL compatible differential signals while the outputs provide PECL/ECL compatible levels with the capability to drive
terminated 50
W transmission lines. The device is pin and function compatible to the MPC991 and is packaged in a 52-lead LQFP
package.
1. Final specification of this parameter is pending characterization.
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
Rev 0
2
FA SUFFIX
52 LEAD LQFP PACKAGE
CASE 848D
MPC9991
3.3V DIFFERENTIAL ECL/PECL
PLL CLOCK GENERATOR
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC9992 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:3.3 DIFFRERENTIAL ECL/PECL PLL CLOCK GENERATOR |
| MPC9992AC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9992ACR2 | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9992FA | 功能描述:鎖相環(huán) - PLL 2.5 3.3V 400MHz Clock Generator RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| MPC9992FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
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