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參數(shù)資料
| 型號： | MPC9991FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 2/11頁 |
| 文件大?。?/td> | 144K |
| 代理商： | MPC9991FA |
MPC9991
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
297
Power Supply Filtering
The MPC9991 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the VCC_PLL power supply impacts the device characteristics,
for instance I/O jitter. The MPC9991 provides separate power
supplies for the output buffers (VCC) and the phase-locked
loop (VCC_PLL) of the device. The purpose of this design tech-
nique is to isolate the high switching noise digital outputs from
the relatively sensitive internal analog phase-locked loop. In a
digital system environment where it is more difficult to minimize
noise on the power supplies a second level of isolation may be
required. The simple but effective form of isolation is a power
supply filter on the VCCA_PLL pin for the MPC9991. Figure 6
illustrates a typical power supply filter scheme. The MPC9991
frequency and phase stability is most susceptible to noise with
spectral content in the 100kHz to 20MHz range. Therefore the
filter should be designed to target this range. The key parame-
ter that needs to be met in the final filter design is the DC volt-
age drop across the series filter resistor RF. From the data
sheet the ICC_PLL current (the current sourced through the
VCC_PLL pin) is typically 3 mA (5 mA maximum), assuming that
a minimum of 2.325V (VCC=3.3V or VCC=2.5V) must be main-
tained on the VCC_PLL pin. The resistor RF shown in Figure 6
“VCC_PLL Power Supply Filter” must have a resistance of
9-10
W (VCC=2.5V) to meet the voltage drop criteria.
Figure 6. VCC_PLL Power Supply Filter
VCC_PLL
VCC
MPC9991
10 nF
RF = 9-10
CF
33...100 nF
RF
VCC
CF = 22 F
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 6 “VCC_PLL Power Supply Filter”, the filter
cut-off frequency is around 3-5 kHz and the noise attenuation
at 100 kHz is better than 42 dB.
As the noise frequency crosses the series resonant point of
an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low im-
pedance path to ground exists for frequencies well above the
bandwidth of the PLL. Although the MPC9991 has several de-
sign features to minimize the susceptibility to power supply
noise (isolated power and grounds and fully differential PLL)
there still may be applications in which overall performance is
being degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be ade-
quate to eliminate power supply noise related problems in
most designs.
Using the MPC9991 in zero–delay applications
Nested clock trees are typical applications for the
MPC9991. Designs using the MPC9991 as LVCMOS PLL fan-
out buffer with zero insertion delay will show significantly lower
clock skew than clock distributions developed from CMOS fan-
out buffers. The external feedback option of the MPC9991
clock driver allows for its use as a zero delay buffer. One exam-
ple configuration is to use a
÷4 output as a feedback to the PLL
and configuring all other outputs to a divide-by-4 mode. The
propagation delay through the device is virtually eliminated.
The PLL aligns the feedback clock output edge with the clock
input reference edge resulting a near zero delay through the
device. The maximum insertion delay of the device in zero-
delay applications is measured between the reference clock
input and any output. This effective delay consists of the static
phase offset, I/O jitter (phase or long-term jitter), feedback path
delay and the output-to-output skew error relative to the feed-
back output.
Calculation of part-to-part skew
The MPC9991 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC9991 are connected together, the maximum overall timing
uncertainty from the common CCLKx input to any output is:
tSK(PP) = t() + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4 components:
static phase offset, output skew, feedback board trace delay
and I/O (phase) jitter:
Figure 7. MPC9991 max. device-to-device skew
tPD,LINE(FB)
tJIT()
+tSK(O)
t()
+t()
tJIT()
+tSK(O)
tSK(PP)
Max. skew
ECLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
Due to the statistical nature of I/O jitter a RMS value (1
s) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 10.
2
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