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參數(shù)資料
| 型號： | MPC9991FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 10/11頁 |
| 文件大?。?/td> | 144K |
| 代理商： | MPC9991FA |
MPC9991
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
295
APPLICATIONS INFORMATION
MPC9991 Configurations
Configuring the MPC9991 amounts to properly configuring
the internal dividers to produce the desired output frequencies.
The output frequency can be represented by this formula:
÷VCO_SEL
÷M
÷N
fREF
fOUT
fOUT = fREF M ÷ N
PLL
where fREF is the reference frequency of the selected input
clock source (ECLK or TCLK), M is the PLL feedback divider
and N is a output divider. M is configured by the FSEL_FB[2:0]
and N is configured for all output banks by the FSEL[3:0] in-
puts.
The reference frequency fREF and the selection of the feed-
back-divider M is limited by the specified VCO frequency
range. fREF and M must be configured to match the VCO fre-
quency range of 800 to 1600 MHz in order to achieve stable
PLL operation:
fVCO,MIN ≤ (fREF VCO_SEL M) ≤ fVCO,MAX
The PLL post-divider VCO_SEL is either a divide-by-two or
a divide-by-four and can be used to situate the VCO into the
specified frequency range. This divider is controlled by the
VCO_SEL pin. VCO_SEL effectively extends the usable input
frequency range while it has no effect on the output to refer-
ence frequency ratio.
The output frequency for each bank can be derived from the
VCO frequency and output divider:
fQA[4:0] = fVCO ÷ (VCO_SEL NA)
fQB[4:0] = fVCO ÷ (VCO_SEL NB)
fQC[3:0] = fVCO ÷ (VCO_SEL NC)
Table 9: MPC9991 Divider
Divider
Function
VCO_SEL
Values
M
PLL feedback
FSEL FB[2 0]
÷2
4, 8, 12, 16, 32, 48, 64
FSEL_FB[2:0]
÷4
8, 16, 24, 32, 64, 96,
128
NA
Bank A Output
Di id
FSEL A
÷2
4, 8, 12, 16
A
Divider FSEL_A
÷4
8, 16, 24, 32
NB
Bank B Output
Di id
FSEL B
÷2
4, 8, 12, 16
B
Divider FSEL_B
÷4
8, 16, 24, 32
NC
Bank C Output
Di id
FSEL C
÷2
4, 8, 12, 16
C
Divider FSEL_C
÷4
8, 16, 24, 32
Table 9 shows the various PLL feedback and output divid-
ers. The output dividers for the three output banks allow the
user to configure the outputs into 1:1, 2:1, 3:1, 3:2, 4:1, 4:3,
4:3:1 and 4:3:2 frequency ratios. Figure 3 and Figure 4 display
example configurations for the MPC9991:
Figure 3. Example Configuration
Figure 4. Example Configuration
MPC9991
fref = 66.6 MHz
200 MHz
66.6 MHz
66.6 MHz (Feedback)
66.6 MHz
MPC9991 example configuration (feedback of
QFB = 66.6 MHz, VCO_SEL=
÷4, M=6, NA=2,
NB=6, NC=6, fVCO=1600 MHz).
Frequency range
Min
Max
Input
33.3 MHz
66.6 MHz
QA outputs
100 MHz
200 MHz
QB outputs
33.3 MHz
66.6 MHz
QC outputs
33.3 MHz
66.6 MHz
ECLK
VCO_SEL
SYNC_SEL
FSEL[3:0]
FSEL_FB[2:0]
QA[3:0]
QB[3:0]
QC[2:0]
QFB
TCLK
REF_SEL
FB_IN
1
0
0100
010
MPC9991
fref = 77.76 MHz
311.04 MHz
155.52 MHz
77.76 MHz (Feedback)
77.76 MHz
MPC9991 example configuration (feedback of
QFB = 77.76 MHz, VCO_SEL=
÷2, M=8, NA=2,
NB=4, NC=8, fVCO=1244.16 MHz).
Frequency range
Min
Max
Input
50 MHz
100 MHz
QA outputs
200 MHz
400 MHz
QB outputs
100 MHz
200 MHz
QC outputs
50 MHz
100 MHz
ECLK
VCO_SEL
SYNC_SEL
FSEL[3:0]
FSEL_FB[2:0]
QA[4:0]
QB[4:0]
QC[3:0]
QFB
TCLK
REF_SEL
FB_IN
1
0110
001
SYNC
QD[1:0]
77.76 MHz
QD[1:0]
QD outputs
50 MHz
100 MHz
2
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