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參數(shù)資料
| 型號： | MPC9991FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | PLASTIC, LQFP-52 |
| 文件頁數(shù)： | 4/11頁 |
| 文件大?。?/td> | 144K |
| 代理商： | MPC9991FA |
MPC9991
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
289
Figure 1. MPC9991 Logic Diagram
0
1
0
1
0
1
4
All input resistors have a value of 50k
0
1
VCC
3
PLL
÷2, ÷4, ÷6, ÷8
QFB
ECLK
TCLK
FSEL[3:0]
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC0
QC1
Bank A
Bank B
Bank C
VCO
Ref
FB
Sync Pulse
÷2, ÷4, ÷6, ÷8
÷16, ÷24, ÷32
÷2, ÷4, ÷6, ÷8
QC2
QD0
FSEL_FB[2:0]
SYNC_SEL
MR
REF_SEL
FB_IN
VCO_SEL
PLL_EN
800-1600 MHz
÷2
÷4
Bank D
÷2, ÷4, ÷6, ÷8
FB_IN
QFB
QD0
QD1
QC0
QC1
QC2
QB0
QB1
QB2
QB3
QA0
QA1
QA2
QA3
FUNCTION TABLE
Control
Default
0
1
REF_SEL
0
Selects ECLK, ECLK as PLL refererence signal
input
Selects TCKL as PLL reference signal input
VCO_SEL
0
Selects VCO
÷2. (high input frequency range)
Selects VCO
÷4. The VCO frequency is scaled by a
factor of 4 (low input frequency range).
PLL_EN
0
Normal operation mode with PLL enabled.
Test mode with the PLL bypassed. The reference clock is
substituted for the internal VCO output. MPC9991 is fully
static and no minimum frequency limit applies. All PLL
related AC characteristics are not applicable.
MR
0
Normal operation
Reset of the device. During reset the PLL feedback loop
is open and the internal VCO is tied to its lowest
frequency. The MPC9991 requires reset at power-up and
after any loss of PLL lock. Loss of PLL lock may occur
when the external feedback path is interrupted. The
length of the reset pulse should be greater than one
reference clock cycle (CCLKx)
SYNC_SEL
0
QD[1:0] outputs generate a SYNC signal
QD[1:0] outputs generate clock signals that match the
QC[2:0] outputs
VCO_SEL, FSEL[3:0] and FSEL_FB[2:0] control the operating PLL frequency range and input/output frequency ratios.
See Table 2 and Table 3 for the device frequency configuration.
2
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| MPC9992FAR2 | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Driver Single 32-Pin LQFP T/R |
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