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參數(shù)資料
| 型號： | MPC97R73FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | LQFP-52 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 252K |
| 代理商： | MPC97R73FA |
MPC97R73
MOTOROLA
TIMING SOLUTIONS
10
MPC97R73 Individual Output Disable (Clock Stop)
Circuitry
The individual clock stop (output enable) control of the
MPC97R73 allows designers, under software control, to
implement power management into the clock distribution
design. A simple serial interface and a clock stop control logic
provides a mechanism through which the MPC97R73 clock
outputs can be individually stopped in the logic ‘0’ state: The
clock stop mechanism allows serial loading of a 12–bit serial
input register. This register contains one programmable clock
stop bit for 12 of the 14 output clocks. The QC0 and QFB
outputs cannot be stopped (disabled) with the serial port.
The user can program an output clock to stop (disable) by
writing logic ‘0’ to the respective stop enable bit. Likewise, the
user may programmably enable an output clock by writing
logic ‘1’ to the respective enable bit. The clock stop logic
enables or disables clock outputs during the time when the
output would be in normally in logic low state, eliminating the
possibility of short or ‘runt’ clock pulses.
The user can write to the serial input register through the
STOP_DATA input by supplying a logic ‘0’ start bit followed
serially by 12 NRZ disable/enable bits. The period of each
STOP_DATA bit equals the period of the free–running
STOP_CLK signal. The STOP_DATA serial transmission
should be timed so the MPC97R73 can sample each
STOP_DATA bit with the rising edge of the free–running
STOP_CLK signal. (see Figure 5. )
Figure 5. Clock Stop Circuit Programming
STOP_CLK
STOP_DATA
START
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
QC1
QC2
QC3
QSYNC
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