- 您現(xiàn)在的位置：買賣IC網 > PDF目錄25632 > MPC97R73FA (MOTOROLA INC) PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 PDF資料下載
參數(shù)資料
| 型號： | MPC97R73FA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封裝： | LQFP-52 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 252K |
| 代理商： | MPC97R73FA |
MPC97R73
MOTOROLA
TIMING SOLUTIONS
12
Power Supply Filtering
The MPC97R73 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Random noise on the VCC_PLL power supply impacts the
device characteristics, for instance I/O jitter. The MPC97R73
provides separate power supplies for the output buffers (VCC)
and the phase-locked loop (VCC_PLL) of the device. The
purpose of this design technique is to isolate the high
switching noise digital outputs from the relatively sensitive
internal analog phase-locked loop. In a digital system
environment where it is more difficult to minimize noise on the
power supplies a second level of isolation may be required.
The simple but effective form of isolation is a power supply
filter on the VCCA_PLL pin for the MPC97R73. Figure 7.
illustrates a typical power supply filter scheme. The
MPC97R73 frequency and phase stability is most
susceptible to noise with spectral content in the 100kHz to
20MHz range. Therefore the filter should be designed to
target this range. The key parameter that needs to be met in
the final filter design is the DC voltage drop across the series
filter resistor RF. From the data sheet the ICC_PLL current (the
current sourced through the VCC_PLL pin) is typically 3 mA (5
mA maximum), assuming that a minimum of 2.325V
(VCC=3.3VorVCC=2.5V)mustbemaintainedontheVCC_PLL
pin. The resistor RF shown in Figure 7. “VCC_PLL Power
Supply Filter” must have a resistance of 9-10
W (VCC=2.5V) to
meet the voltage drop criteria.
Figure 7. VCC_PLL Power Supply Filter
VCC_PLL
VCC
MPC97R7
3
10 nF
RF = 9–10
CF
33...100 nF
RF
VCC
CF = 22 F
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 7. “VCC_PLL Power Supply Filter”, the
filter cut-off frequency is around 3-5 kHz and the noise
attenuation at 100 kHz is better than 42 dB.
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC97R73 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
Using the MPC97R73 in zero–delay applications
Nested clock trees are typical applications for the
MPC97R73. Designs using the MPC97R73 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC97R73 clock driver allows for its use as a zero delay
buffer. One example configuration is to use a
÷4 output as a
feedback to the PLL and configuring all other outputs to a
divide-by-4 mode. The propagation delay through the device
is virtually eliminated. The PLL aligns the feedback clock
output edge with the clock input reference edge resulting a
near zero delay through the device. The maximum insertion
delay of the device in zero-delay applications is measured
between the reference clock input and any output. This
effective delay consists of the static phase offset, I/O jitter
(phase or long-term jitter), feedback path delay and the
output-to-output skew error relative to the feedback output.
Calculation of part-to-part skew
The MPC97R73 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC97R73 are connected together, the maximum overall
timing uncertainty from the common CCLKx input to any
output is:
tSK(PP) = t(
) + tSK(O) + tPD, LINE(FB) + tJIT() CF
This maximum timing uncertainty consist of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
Figure 8. MPC97R73 max. device-to-device skew
tPD,LINE(FB)
tJIT(
)
+tSK(O)
–t(
)
+t(
)
tJIT(
)
+tSK(O)
tSK(PP)
Max. skew
CCLKCommon
QFBDevice 1
Any QDevice 1
QFBDevice2
Any QDevice 2
Due to the statistical nature of I/O jitter a RMS value (1
s) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 14.
相關PDF資料 |
PDF描述 |
|---|---|
| MPC9892FA | PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32 |
| MPC9991FA | PLL BASED CLOCK DRIVER, 13 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| MQ80C154-16P883R | 8-BIT, 16 MHz, MICROCONTROLLER, CQFP44 |
| 952100202 | 8-BIT, 30 MHz, MICROCONTROLLER, CQCC44 |
| MD80C52EXXX-30SBD | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CDIP40 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC980 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:DUAL 3.3V PLL CLOCK GENERATOR |
| MPC9817 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Clock Generator for PowerQUICC and PowerPC Microprocessors and Microcontrollers |
| MPC9817EN | 功能描述:時鐘發(fā)生器及支持產品 FSL 1-5 PwrQUICC/Pwr PC Clk Gen, RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9817ENR2 | 功能描述:時鐘發(fā)生器及支持產品 FSL 1-5 PwrQUICC/Pwr PC Clk Gen, RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MPC9817SD | 功能描述:時鐘發(fā)生器及支持產品 FSL 1-5 PwrQUICC/Pwr PC Clk Gen, RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購，3分鐘左右您將得到回復。