參數(shù)資料
型號(hào): MPC8308CVMAFD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA473
封裝: 19 X 19 MM, 0.80 MM PITCH, 1.39 MM HEIGHT, LEAD FREE, MAPBGA-473
文件頁數(shù): 88/88頁
文件大?。?/td> 2550K
代理商: MPC8308CVMAFD
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1
Freescale Semiconductor
9
RESET Initialization
5.2
RESET AC Electrical Characteristics
Table 11 provides the reset initialization AC timing specifications.
Table 12 provides the PLL lock times.
Output low voltage
VOL
IOL = 8.0 mA
0.5
V
Output low voltage
VOL
IOL = 3.2 mA
0.4
V
Table 11. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET (input) to activate reset flow
32
tSYS_CLK_IN
1
Required assertion time of PORESET with stable power and clock applied to
SYS_CLK_IN
32
tSYS_CLK_IN
HRESET assertion (output)
512
tSYS_CLK_IN
1
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]) with
respect to negation of PORESET
4—
tSYS_CLK_IN
Input hold time for POR configuration signals with respect to negation of HRESET
0—
ns
Time for the device to turn off POR configuration signal drivers with respect to the
assertion of HRESET
—4
ns
2
Time for the device to turn on POR configuration signal drivers with respect to the
negation of HRESET
1
ns
1, 2
Notes:
1. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN
2. POR configuration signals consists of CFG_RESET_SOURCE[0:3]
Table 12. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
System PLL lock time
100
μs—
e300 core PLL lock time
100
μs—
Table 10. RESET Pins DC Electrical Characteristics (continued)
Characteristic
Symbol
Condition
Min
Max
Unit
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