參數(shù)資料
型號： MPC8308CVMAFD
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 266 MHz, MICROPROCESSOR, PBGA473
封裝： 19 X 19 MM, 0.80 MM PITCH, 1.39 MM HEIGHT, LEAD FREE, MAPBGA-473
文件頁數(shù)： 10/88頁
文件大?。?/td> 2550K
代理商： MPC8308CVMAFD
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1
18
Freescale Semiconductor
Ethernet: Three-Speed Ethernet, MII Management
Figure 9 shows the MII receive AC timing diagram.
Figure 9. MII Receive AC Timing Diagram RMII AC Timing Specifications
Figure 10 provides the AC test load.
Figure 10. AC Test Load
8.2.2
RGMII AC Timing Specifications
Table 25 presents the RGMII AC timing specifications.
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
tMRDXKH
10.0
—
ns
RX_CLK clock rise VIL(min) to VIH(max)
tMRXR
1.0—
4.0ns
RX_CLK clock fall time VIH(max) to VIL(min)
tMRXF
1.0—
4.0ns
Note:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII
receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference
(K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data
input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
Table 25. RGMII AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V ± 5%.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Data to clock output skew (at transmitter)
tSKRGT
–0.6
—
0.6
ns
Data to clock input skew (at receiver) 2
tSKRGT
1.0
—
2.6
ns
Table 24. MII Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDD /NVDD of 3.3 V ± 0.3V.
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
RX_CLK
RXD[3:0]
tMRDXKH
tMRX
tMRXH
tMRXR
tMRXF
RX_DV
RX_ER
tMRDVKH
Valid Data
Output
Z0 = 50 Ω
NVDD/2
RL = 50 Ω
or
LVDD/2
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