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參數(shù)資料
| 型號： | MPC755BRX300LX |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 7/48頁 |
| 文件大?。?/td> | 1265K |
| 代理商： | MPC755BRX300LX |
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MPC755 RISC Microprocessor Hardware Specifications
15
Electrical and Thermal Characteristics
Figure 6. Input/Output Timing Diagram
1.4.2.3 L2 Clock AC Specifications
The L2CLK frequency is programmed by the L2 Configuration Register (L2CR[4-6]) core-to-L2 divisor
ratio. See Table 17 for example core and L2 frequencies at various divisors. Table 11 provides the potential
range of L2CLK output AC timing specifications as defined in Figure 7.
The minimum L2CLK frequency of Table 11 is specified by the maximum delay of the internal DLL. The
variable-tap DLL introduces up to a full clock period delay in the L2CLKOUTA, L2CLKOUTB, and
L2SYNC_OUT signals so that the returning L2SYNC_IN signal is phase aligned with the next core clock
(divided by the L2 divisor ratio). Do not choose a core-to-L2 divisor which results in an L2 frequency below
this minimum, or the L2CLKOUT signals provided for SRAM clocking will not be phase aligned with the
MPC755 core clock at the SRAMs.
The maximum L2CLK frequency shown in Table 11 is the core frequency divided by one. Very few L2
SRAM designs will be able to operate in this mode. Most designs will select a greater core-to-L2 divisor to
provide a longer L2CLK period for read and write access to the L2 SRAMs. The maximum L2CLK
frequency for any application of the MPC755 will be a function of the AC timings of the MPC755, the AC
timings for the SRAM, bus loading, and printed circuit board trace length. The current AC timing of the
MPC755 supports up to 200 MHz with typical, similarly-rated SRAM parts, provided careful design
practices are observed. Clock trace lengths must be matched and all trace lengths should be as short as
possible. Higher frequencies can be achieved by using better performing SRAM. Note: Revisions of the
MPC755 prior to Rev 2.8 (Rev E) were limited in performance, and were typically limited to 175 MHz with
similarly-rated SRAM. For more information, contact your local Motorola sales office.
Motorola is similarly limited by system constraints and cannot perform tests of the L2 interface on a
SYSCLK
ALL INPUTS
VM
VM = Midpoint Voltage (OVDD/2 or Vin/2)
ALL OUTPUTS
tKHOX
VM
(Except TS, ABB,
ARTRY, DBB)
TS,ABB,DBB
ARTRY
VM
tKHOZ
tKHABPZ
tKHARPZ
tKHARP
tKHOV
tKHOX
tKHOV
tKHOX
tKHOV
tIVKH
tKHOE
tIXKH
tKHOZ
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| MPC755BRX350LE | 功能描述:微處理器 - MPU 360CBGA,RV2.8,HIP4DP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC755BRX350TE | 功能描述:微處理器 - MPU 360CBGA,RV2.8,HIP4DP RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC755BVT300LE | 功能描述:微處理器 - MPU RV2.8106C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC755BVT350LE | 功能描述:微處理器 - MPU RV2.8,106C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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