參數(shù)資料
型號: MPC755BRX300LX
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 3.20 MM HEIGHT, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù): 29/48頁
文件大?。?/td> 1265K
代理商: MPC755BRX300LX
MPC755 RISC Microprocessor Hardware Specifications
35
System Design Information
1.8.2 PLL Power Supply Filtering
The AVdd and L2AVdd power signals are provided on the MPC755 to provide power to the clock generation
phase-locked loop and L2 cache delay-locked loop respectively. To ensure stability of the internal clock, the
power supplied to the AVdd input signal should be filtered of any noise in the 500 kHz to 10 MHz resonant
frequency range of the PLL. A circuit similar to the one shown in Figure 21 using surface mount capacitors
with minimum Effective Series Inductance (ESL) is recommended. Consistent with the recommendations
of Dr. Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993),
multiple small capacitors of equal value are recommended over a single large value capacitor.
The circuit should be placed as close as possible to the AVdd pin to minimize noise coupled from nearby
circuits. An identical but separate circuit should be placed as close as possible to the L2AVdd pin. It is often
possible to route directly from the capacitors to the AVdd pin, which is on the periphery of the 360 BGA
footprint, without the inductance of vias. The L2AVdd pin may be more difficult to route, but is
proportionately less critical.
FIgure 21 shows the PLL power supply filter circuit.
Figure 21. PLL Power Supply Filter Circuit
1.8.3 Power Supply Voltage Sequencing
The notes in Figure 1 contain cautions about the sequencing of the external bus voltages and core voltage
of the MPC755 (when they are different). These cautions are necessary for the long term reliability of the
part. If they are violated, the ESD (Electrostatic Discharge) protection diodes will be forward biased and
excessive current can flow through these diodes. If the system power supply design does not control the
voltage sequencing, the circuit of Figure 22 can be added to meet these requirements. The MURS320
Schottky diodes of Figure 22 control the maximum potential difference between the external bus and core
power supplies on power-up and the 1N5820 diodes regulate the maximum potential difference on
power-down.
Figure 22. Example Voltage Sequencing Circuit
1.8.4 Decoupling Recommendations
Due to the MPC755 dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC755 can generate transient power surges and high frequency noise in its power supply,
Vdd
AVdd (or L2AVdd)
10
2.2 F
GND
Low ESL surface mount capacitors
3.3 V
2.0 V
MURS320
1N5820
MURS320
1N5820
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