參數(shù)資料
型號(hào)： MM908E630CVFC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, QCC44
封裝： 9 X 9 MM, 1 MM HEIGHT, 0.65 MM PITCH, ROHS COMPLIANT, QFN-44
文件頁(yè)數(shù)： 6/48頁(yè)
文件大?。?/td> 2299K
代理商： MM908E630CVFC
Analog Integrated Circuit Device Data
14
Freescale Semiconductor
908E630
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
All characteristics are for the analog die only. Refer to the 68HC908EY16A datasheet for characteristics of the microcontroller
die. Characteristics noted under conditions 5.5 V
≤ VSUP ≤ 18 V, -40°C ≤ TJ ≤ 125°C, unless otherwise noted. Typical values
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI INTERFACE TIMING
SPI Operating Frequency
fSPIOP
4.0
MHz
RESET OUTPUT PIN (RST_A)
Reset Low-level Duration after VDD High (SEE Figure 11, PAGE 19)
tRST_A
0.65
1.0
1.35
ms
Reset Deglitch Filter Time
tRST_ADF
350
480
900
ns
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)
Watchdog Time Period(42)
External Resistor REXT = 20 kΩ (1%)
External Resistor REXT = 200 kΩ (1%)
Without External Resistor REXT (WDCONF Pin Open)
tPWD
8.5
79
110
10
94
150
11.5
108
205
ms
CURRENT SENSE AMPLIFIER(43)
Common Mode Rejection Ratio
CMR
70
dB
Supply Voltage Rejection Ratio(44)
SVR
60
dB
Gain Bandwidth Product
GBP
0.75
3.0
MHz
Output Slew Rate
SR
0.5
V/s
DIGITAL/ANALOG INPUT PINS (L1, L2, L3 AND L4)
Wake-up Filter Time
tWUF
8.0
20
38
μs
STATE MACHINE TIMING
Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)
and Stop Mode Activation(43)
tSTOP
5.0
μs
Normal Request Mode Time-out (SEE Figure 11, PAGE 19
)
tNRTOUT
110
150
205
ms
Delay Between SPI Command and HS/LS Turn On(45) (9.0 V < VSUP < 27 V)
tS-ON
10
μs
Delay Between SPI Command and HS/LS Turn Off(45) (9.0 V < VSUP < 27 V)
tS-OFF
10
μs
Delay Between Normal Request and Normal Mode After a Watchdog Trigger
Command (Normal Request Mode)(43)
tSNR2N
10
μs
Delay Between CS Wake-up (CS LOW to HIGH) in Stop Mode and:
Normal Request Mode, VDD ON and RST_A HIGH
First Accepted SPI Command
tWUCS
tWUSPI
9.0
90
15
80
μs
Minimum Time Between Rising and Falling Edge on the CS
t2CS
4.0
μs
J2606 DEGLITCHER
VSUP Deglitcher(46)
(DIS_J2602 = 0)
tJ2602_DEG
35
50
70
μs
Notes
42.
Watchdog timing period calculation formula: tPWD [ms] = 0.466 * (REXT - 20) + 10 (REXT in kΩ).
43.
This parameter is guaranteed by process monitoring but not production tested.
44.
Analog Outputs are supplied by VDD
45.
Delay between turn on or off command (rising edge on CS) and HS or LS ON or OFF, excluding rise or fall time due to external load.
46.
This parameter was not monitored during operating life test.
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