參數(shù)資料
型號(hào)： MM908E630CVFC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, QCC44
封裝： 9 X 9 MM, 1 MM HEIGHT, 0.65 MM PITCH, ROHS COMPLIANT, QFN-44
文件頁數(shù)： 39/48頁
文件大?。?/td> 2299K
代理商： MM908E630CVFC
Analog Integrated Circuit Device Data
44
Freescale Semiconductor
908E630
INTEGRATED DUAL LOW & HIDE-SIDE SWITCH
THERMAL ADDENDUM (REV. 1.0)
INTEGRATED DUAL LOW & HIDE-SIDE SWITCH
THERMAL ADDENDUM (REV. 1.0)
Introduction
This thermal addendum is provided as a supplement to the 908E630 technical
data sheet. The addendum provides thermal performance information that may
be critical in the design and development of system applications. All electrical,
application and packaging information is provided in the data sheet.
Package and Thermal Considerations
The 908E630 is a dual die package. There are two heat sources in the
package independently heating with P1 and P2. This results in two junction
temperatures, TJ1 and TJ2, and a thermal resistance matrix with RθJAmn.
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference
temperature while only heat source 1 is heating with P1.
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the
reference temperature while heat source 2 is heating with P2. This applies to
RθJ21 and RθJ22, respectively.
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment.
This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated
values were obtained by measurement and simulation according to the standards listed below.
44-PIN QFN-EP
908E630CVFC
FC SUFFIX
98ASA10742D
44-PIN QFN-EP
Note
For package dimensions, refer to the
908E630 device datasheet.
TJ1
TJ2
=
RθJA11
RθJA21
RθJA12
RθJA22
.
P1
P2
Figure 22. Thermal Land Pattern for Direct Thermal
Attachment per JEDEC JESD51-5
Table 32. Thermal Performance Comparison
Thermal
Resistance
1 = Power Chip, 2 = Logic Chip
[
°C/W]
m = 1,
n = 1
m = 1, n = 2
m = 2, n = 1
m = 2,
n = 2
RθJAmn
49
20
22
RθJBmn
35
6
8
RθJAmn
82
50
52
RθJCmn
24
0
0.5
Notes:
1.
Per JEDEC JESD51-2 at natural convection, still air
condition.
2.
2s2p thermal test board per JEDEC JESD51-7 and
JESD51-5.
3.
Per JEDEC JESD51-8, with the board temperature on the
center trace near the power outputs.
4.
Single layer thermal test board per JEDEC JESD51-3 and
JESD51-5.
5.
Thermal resistance between the die junction and the
exposed pad, “infinite” heat sink attached to exposed pad.
1.0
0.2
44-Terminal QFN-EP
0.65 mm Pitch
9.0 x 9.0 mm Body
7.2 x 7.2 mm Exposed Pad
All measurements
are in millimeter
Solder mask
opening
Thermal vias
connected to top
buried plane
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