參數(shù)資料
型號(hào)： MM908E630CVFC
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： MICROCONTROLLER, QCC44
封裝： 9 X 9 MM, 1 MM HEIGHT, 0.65 MM PITCH, ROHS COMPLIANT, QFN-44
文件頁(yè)數(shù)： 32/48頁(yè)
文件大小： 2299K
代理商： MM908E630CVFC
Analog Integrated Circuit Device Data
38
Freescale Semiconductor
908E630
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LSxCL - Low Side Current Limitation
This read-only bit indicates that the respective Low Side
switch is operating in current limitation mode.
1 = LSx in current limitation (or thermal shutdown)
0 = Normal
Timing Control Register - TIMCR
This register is a double purpose register which allows to
configure the watchdog and the cyclic sense periods. Writing
to the Timing Control Register will also return the Watchdog
Status Register WDSR.
CS/WD - Cyclic Sense or Watchdog prescaler select.
This write-only bit selects which prescaler is being written
to, the Cyclic Sense prescaler or the Watchdog prescaler.
1 = Cyclic Sense Prescaler selected
0 = Watchdog Prescaler select
WDx - Watchdog Prescaler
This write-only bits selects the divider for the watchdog
prescaler and therefore selects the watchdog period in
accordance with Table 23. This configuration is valid only if
windowing watchdog is active.
Table 23. Watchdog Prescaler
CYSTx - Cyclic Sense Period Prescaler Select
This write-only bits selects the interval for the wake-up
cyclic sensing together with the bit CYSX8 in the
Configuration Register (See Configuration Register - CFR).
This option is only active if one of the High Side switches
is enabled when entering in Stop or Sleep mode. Otherwise
a timed wake-up is performed after the period shown in
Table 24. Cyclic Sense Interval
Watchdog Status Register - WDSR
This register returns the Watchdog status information and
is also returned when writing to the Timing Control Register
TIMCR.
WDTO - Watchdog Time Out
This read-only bit signals the last reset was caused by
either a watchdog timeout or by an attempt to clear the
watchdog within the window closed.
Any access to this register or the Timing Control Register
TIMCR will clear the WDTO bit.
1 = Last reset caused by watchdog timeout
0 = None
WDERR - Watchdog Error
This read-only bit signals the detection of a missing
watchdog resistor. In this condition the watchdog is using the
internal, lower precision time-base. The windowing function
is disabled.
1 = WDCONF pin resistor missing
0 = WDCONF pin resistor not floating
Table 22. Timing Control Register - $A
C3
C2
C1
C0
Write
CS/WD
WD2
WD1
WD0
CYST2
CYST1
CYST0
Reset
Value
-
000
Reset
Condition
-POR
WD2
WD1
WD0
Prescaler Divider
0
1
0
1
2
0
1
0
4
0
1
6
1
0
8
1
0
1
10
1
0
12
1
14
CYSX8(58)
CYST2
CYST1
CYST0
Meaning
X
0
No cyclic sense
0
1
20ms
0
1
0
40ms
0
1
60ms
0
1
0
80ms
0
1
0
1
100ms
0
1
0
120ms
0
1
140ms
1
0
1
160ms
1
0
1
0
320ms
1
0
1
480ms
1
0
640ms
1
0
1
800ms
1
0
960ms
1
1120ms
Notes
58.
bit CYSX8 is located in Configuration Register CFR
Table 25. Watchdog Status Register - $A/$B
S3
S2
S1
S0
Read
WDTO
WDERR
WDOFF
WDWO
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