參數(shù)資料
型號: ML610Q412P-XXXWA
廠商: LAPIS SEMICONDUCTOR CO LTD
元件分類: 微控制器/微處理器
英文描述: RISC MICROCONTROLLER, UUC95
封裝: 2.83 MM X 2.63 MM, 0.35 MM HEIGHT, 0.80 MM PITCH, DIE-95
文件頁數(shù): 56/152頁
文件大?。?/td> 1641K
代理商: ML610Q412P-XXXWA
ML610Q411/ML610Q412/ML610Q415 User’s Manual
Chapter 10
Timers
10 – 22
(4) Set “FFH” to both TM2D register and TM3D register.
(5) Clear both TM2C register and TM3C register to “00H”.
(6) Set T2RUN bit (bit0 of TM2CON1 register) to “1” to start counting the timer.
(7) On the condition of (T23MFM rbg =="1") & ((TM23M16 rbg =="1") & (T2RUN rbg =="1"), the
count-up starts at rising edge of 64Hz clock signal.
(8) The count-up stops at the falling edge of the next timer clock (HTBCLK) after 437C signal becomes “1”.
Also, at the same time, T2RUN bit and T2STAT bit become “0” and the interrupt signal TM3INT activates.
(9) After checking T2STAT bit or TM3INT interrupt occurs, read out the data (N1) of TM2C register and
TM3C register.
For example of utilizing N1, to occur 9600Hz timer interrupt.
Assuming the HTBCLK is 600kHz,
N1 = 600000 * 437 / 32768
= 8001 (Decimal)
= 1F41 (Hexadecimal)
= 0001 1111 0100 0001 (Binary)
As (437 / 32768) sec is equivalent to 128 clocks at 9600Hz (more precisely, 9598Hz), a division of the count N1
by 128 equals frequency ratio (N2) between the frequency of HTBCLK and 9600Hz.
Because 128 = 2
7, that caluculation can be determined by truncating the righthand seven digits of N1(Binary).
N2 = 8001(Decimal) / 128 (Decimal)
=0001 1111 0 (Binary)
=3E (Hexadecimal)
=62 (Decimal)
This indicates that 9600Hz is about 62 times the cycle of HTBCLK.
Therefore, if 3DH(=3EH-1) set to the timer register and the timer start counting, the cycle of TMnINT interrupt
that can occur every 62 counts of HTBCLK is:
tTMnINT = (1 / 600000) * 62 = 0.10333ms (9677Hz)
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