參數(shù)資料
型號(hào)： ML610Q412P-XXXWA
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, UUC95
封裝： 2.83 MM X 2.63 MM, 0.35 MM HEIGHT, 0.80 MM PITCH, DIE-95
文件頁數(shù)： 132/152頁
文件大?。?/td> 1641K
代理商： ML610Q412P-XXXWA
ML610Q411/ML610Q412/ML610Q415 User’s Manual
Chapter 5
Interrupts (INTs)
5 – 19
5.3.1
Maskable Interrupt Processing
When an interrupt is generated with the MIE flag set to “1”, the following processing is executed by hardware and the
processing of program shifts to the interrupt destination.
(1) Transfer the program counter (PC) to ELR1.
(2) Transfer CSR to ECSR1.
(3) Transfer PSW toEPSW1.
(4) Set the MIE flag to “0”.
(5) Set the ELEVEL field to“1”.
(6) Load the interrupt start address into PC.
5.3.2
Non-Maskable Interrupt Processing
When an interrupt is generated regardless of the state of MIE flag, the following processing is performed by hardware
and the processing of program shifts to the interrupt destination.
(1) Transfer PC to ELR2.
(2) Transfer CSR to ECSR2.
(3) Transfer PSW to EPSW2.
(4) Set the ELEVEL field to “2”.
(5) Load the interrupt start address into PC.
5.3.3
Software Interrupt Processing
A software interrupt is generated as required within an application program. When the SWI instruction is performed
within the program, a software interrupt is generated, the following processing is performed by hardware, and the
processing program shifts to the interrupt destination.
The vector table is specified by the SWI instruction.
(1) Transfer PC to ELR1.
(2) Transfer CSR to ECSR1.
(3) Transfer PSW to EPSW1.
(4) Set the MIE flag to “0”.
(5) Set the ELEVEL field to “1”.
(6) Load the interrupt start address into PC.
Reference:
For the MIE flag, Program Counter (PC), CSR, PSW, and ELEVEL, see “nX-U8/100 Core Instruction Manual”.
相關(guān)PDF資料
PDF描述
ML610Q411-XXXWA RISC MICROCONTROLLER, UUC95
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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