參數(shù)資料
型號： ML610Q412P-XXXWA
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, UUC95
封裝： 2.83 MM X 2.63 MM, 0.35 MM HEIGHT, 0.80 MM PITCH, DIE-95
文件頁數(shù)： 42/152頁
文件大?。?/td> 1641K
代理商： ML610Q412P-XXXWA
ML610Q411/ML610Q412/ML610Q415 User’s Manual
Chapter 10
Timers
10 – 9
10.2.7
Timer 1 Counter Register (TM1C)
Address: 0F035H
Access: R/W
Access size: 8 bits
Initial value: 00H
7
6
5
4
3
2
1
0
TM1C
T1C7
T1C6
T1C5
T1C4
T1C3
T1C2
T1C1
T1C0
R/W
Initial value
0
TM1C is a special function register (SFR) that functions as an 8-bit binary counter.
When write operation to TM1C is performed, TM1C is set to “00H”. The data that is written is meaningless.
In 16-bit timer mode and 16-bit timer frequency measurement mode, if write operation is performed to either the
low-order TM0C or high-order TM1C, both the low order and the high order are set to “0000H”.
When reading TM1C in 16-bit timer mode, be sure to read TM0C first since the count value of TM1C is stored in the
TM1C latch when TM0C is read.
During timer operation, the contents of TM1C may not be read depending on the conditions of the timer clock and the
system clock.
Table 10-2 shows whether a TM1C read is enabled or disabled during timer operation for each condition of the timer
clock and system clock.
Table 10-2
TM1C Read Enable/Disable during Timer Operation
Timer clock
T1CK
System clock
SYSCLK
TM1C read enable/disable
LSCLK
Read enabled
LSCLK
HSCLK
Read enabled.
However, to prevent the reading of undefined
data during incremental counting, read TM1C twice and check
that the results match.
HTBCLK
LSCLK
Read disabled
HTBCLK
HSCLK
Read enabled
LSCLK
External clock
HSCLK
Read disabled
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PDF描述
ML610Q411-XXXWA RISC MICROCONTROLLER, UUC95
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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